1007a7a33SSumit Garg /* 2007a7a33SSumit Garg * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3007a7a33SSumit Garg * 4007a7a33SSumit Garg * SPDX-License-Identifier: BSD-3-Clause 5007a7a33SSumit Garg */ 6007a7a33SSumit Garg 7007a7a33SSumit Garg #include <platform_def.h> 8007a7a33SSumit Garg 9*09d40e0eSAntonio Nino Diaz #include <arch.h> 10*09d40e0eSAntonio Nino Diaz 11*09d40e0eSAntonio Nino Diaz #include <sq_common.h> 12*09d40e0eSAntonio Nino Diaz 13007a7a33SSumit Garg unsigned char sq_pd_tree_desc[PLAT_CLUSTER_COUNT + 1]; 14007a7a33SSumit Garg plat_core_pos_by_mpidr(u_register_t mpidr)15007a7a33SSumit Gargint plat_core_pos_by_mpidr(u_register_t mpidr) 16007a7a33SSumit Garg { 17007a7a33SSumit Garg unsigned int cluster_id, cpu_id; 18007a7a33SSumit Garg 19007a7a33SSumit Garg cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; 20007a7a33SSumit Garg if (cluster_id >= PLAT_CLUSTER_COUNT) 21007a7a33SSumit Garg return -1; 22007a7a33SSumit Garg 23007a7a33SSumit Garg cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; 24007a7a33SSumit Garg if (cpu_id >= PLAT_MAX_CORES_PER_CLUSTER) 25007a7a33SSumit Garg return -1; 26007a7a33SSumit Garg 27007a7a33SSumit Garg return sq_calc_core_pos(mpidr); 28007a7a33SSumit Garg } 29007a7a33SSumit Garg plat_get_power_domain_tree_desc(void)30007a7a33SSumit Gargconst unsigned char *plat_get_power_domain_tree_desc(void) 31007a7a33SSumit Garg { 32007a7a33SSumit Garg int i; 33007a7a33SSumit Garg 34007a7a33SSumit Garg sq_pd_tree_desc[0] = PLAT_CLUSTER_COUNT; 35007a7a33SSumit Garg 36007a7a33SSumit Garg for (i = 0; i < PLAT_CLUSTER_COUNT; i++) 37007a7a33SSumit Garg sq_pd_tree_desc[i + 1] = PLAT_MAX_CORES_PER_CLUSTER; 38007a7a33SSumit Garg 39007a7a33SSumit Garg return sq_pd_tree_desc; 40007a7a33SSumit Garg } 41