180d37c28SDeepak Pandey/* 2da6d75a0SJohn Tsichritzis * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. 380d37c28SDeepak Pandey * 480d37c28SDeepak Pandey * SPDX-License-Identifier: BSD-3-Clause 580d37c28SDeepak Pandey */ 680d37c28SDeepak Pandey 780d37c28SDeepak Pandey#include <arch.h> 880d37c28SDeepak Pandey#include <asm_macros.S> 9da6d75a0SJohn Tsichritzis#include <neoverse_n1.h> 1080d37c28SDeepak Pandey#include <cpu_macros.S> 1180d37c28SDeepak Pandey#include <platform_def.h> 1280d37c28SDeepak Pandey 1380d37c28SDeepak Pandey .globl plat_arm_calc_core_pos 1480d37c28SDeepak Pandey .globl plat_reset_handler 1580d37c28SDeepak Pandey 1680d37c28SDeepak Pandey /* ----------------------------------------------------- 1780d37c28SDeepak Pandey * unsigned int plat_arm_calc_core_pos(u_register_t mpidr) 1880d37c28SDeepak Pandey * 1980d37c28SDeepak Pandey * Helper function to calculate the core position. 20*f91a8e4cSManish Pandey * ((ChipId * N1SDP_MAX_CLUSTERS_PER_CHIP + ClusterId) * 21*f91a8e4cSManish Pandey * N1SDP_MAX_CPUS_PER_CLUSTER * N1SDP_MAX_PE_PER_CPU) + 22*f91a8e4cSManish Pandey * (CPUId * N1SDP_MAX_PE_PER_CPU) + ThreadId 2380d37c28SDeepak Pandey * 2480d37c28SDeepak Pandey * which can be simplified as: 2580d37c28SDeepak Pandey * 26*f91a8e4cSManish Pandey * (((ChipId * N1SDP_MAX_CLUSTERS_PER_CHIP + ClusterId) * 27*f91a8e4cSManish Pandey * N1SDP_MAX_CPUS_PER_CLUSTER + CPUId) * N1SDP_MAX_PE_PER_CPU) + 28*f91a8e4cSManish Pandey * ThreadId 2980d37c28SDeepak Pandey * ------------------------------------------------------ 3080d37c28SDeepak Pandey */ 3180d37c28SDeepak Pandey 3280d37c28SDeepak Pandeyfunc plat_arm_calc_core_pos 33*f91a8e4cSManish Pandey mov x4, x0 3480d37c28SDeepak Pandey 3580d37c28SDeepak Pandey /* 3680d37c28SDeepak Pandey * The MT bit in MPIDR is always set for n1sdp and the 3780d37c28SDeepak Pandey * affinity level 0 corresponds to thread affinity level. 3880d37c28SDeepak Pandey */ 3980d37c28SDeepak Pandey 4080d37c28SDeepak Pandey /* Extract individual affinity fields from MPIDR */ 41*f91a8e4cSManish Pandey ubfx x0, x4, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS 42*f91a8e4cSManish Pandey ubfx x1, x4, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS 43*f91a8e4cSManish Pandey ubfx x2, x4, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS 44*f91a8e4cSManish Pandey ubfx x3, x4, #MPIDR_AFF3_SHIFT, #MPIDR_AFFINITY_BITS 4580d37c28SDeepak Pandey 4680d37c28SDeepak Pandey /* Compute linear position */ 47*f91a8e4cSManish Pandey mov x4, #N1SDP_MAX_CLUSTERS_PER_CHIP 48*f91a8e4cSManish Pandey madd x2, x3, x4, x2 4980d37c28SDeepak Pandey mov x4, #N1SDP_MAX_CPUS_PER_CLUSTER 5080d37c28SDeepak Pandey madd x1, x2, x4, x1 51*f91a8e4cSManish Pandey mov x4, #N1SDP_MAX_PE_PER_CPU 52*f91a8e4cSManish Pandey madd x0, x1, x4, x0 5380d37c28SDeepak Pandey ret 5480d37c28SDeepak Pandeyendfunc plat_arm_calc_core_pos 5580d37c28SDeepak Pandey 5680d37c28SDeepak Pandey /* ----------------------------------------------------- 5780d37c28SDeepak Pandey * void plat_reset_handler(void); 5880d37c28SDeepak Pandey * 5980d37c28SDeepak Pandey * Determine the CPU MIDR and disable power down bit for 6080d37c28SDeepak Pandey * that CPU. 6180d37c28SDeepak Pandey * ----------------------------------------------------- 6280d37c28SDeepak Pandey */ 6380d37c28SDeepak Pandey 6480d37c28SDeepak Pandeyfunc plat_reset_handler 65da6d75a0SJohn Tsichritzis jump_if_cpu_midr NEOVERSE_N1_MIDR, N1 6680d37c28SDeepak Pandey ret 6780d37c28SDeepak Pandey 6880d37c28SDeepak Pandey /* ----------------------------------------------------- 6980d37c28SDeepak Pandey * Disable CPU power down bit in power control register 7080d37c28SDeepak Pandey * ----------------------------------------------------- 7180d37c28SDeepak Pandey */ 72da6d75a0SJohn TsichritzisN1: 73da6d75a0SJohn Tsichritzis mrs x0, NEOVERSE_N1_CPUPWRCTLR_EL1 74da6d75a0SJohn Tsichritzis bic x0, x0, #NEOVERSE_N1_CORE_PWRDN_EN_MASK 75da6d75a0SJohn Tsichritzis msr NEOVERSE_N1_CPUPWRCTLR_EL1, x0 7680d37c28SDeepak Pandey isb 7780d37c28SDeepak Pandey ret 7880d37c28SDeepak Pandeyendfunc plat_reset_handler 79