1 /*
2 * Copyright (c) 2025, Renesas Electronics Corporation. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <common/debug.h>
8 #include <lib/psci/psci.h>
9
10 #include <plat_helpers.h>
11 #include <platform_def.h>
12 #include "rcar_private.h"
13 #include "rcar_scmi_id.h"
14
plat_get_power_domain_tree_desc(void)15 const unsigned char *plat_get_power_domain_tree_desc(void)
16 {
17 static const unsigned char rcar_power_domain_tree_desc[] = {
18 1,
19 PLATFORM_CLUSTER_COUNT,
20 PLATFORM_CLUSTER0_CORE_COUNT,
21 PLATFORM_CLUSTER1_CORE_COUNT,
22 PLATFORM_CLUSTER2_CORE_COUNT,
23 PLATFORM_CLUSTER3_CORE_COUNT,
24 PLATFORM_CLUSTER4_CORE_COUNT,
25 PLATFORM_CLUSTER5_CORE_COUNT,
26 PLATFORM_CLUSTER6_CORE_COUNT,
27 PLATFORM_CLUSTER7_CORE_COUNT
28 };
29
30 return rcar_power_domain_tree_desc;
31 }
32
33 /*******************************************************************************
34 * The array mapping platform core position (implemented by plat_my_core_pos())
35 * to the SCMI power domain ID implemented by SCP.
36 ******************************************************************************/
37 const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[] = {
38 (SET_SCMI_CHANNEL_ID(0x0) | SCP_POWER_DOMAIN_ID_PD_P_APU_CORE00),
39 (SET_SCMI_CHANNEL_ID(0x0) | SCP_POWER_DOMAIN_ID_PD_P_APU_CORE01),
40 (SET_SCMI_CHANNEL_ID(0x0) | SCP_POWER_DOMAIN_ID_PD_P_APU_CORE02),
41 (SET_SCMI_CHANNEL_ID(0x0) | SCP_POWER_DOMAIN_ID_PD_P_APU_CORE03),
42 (SET_SCMI_CHANNEL_ID(0x0) | SCP_POWER_DOMAIN_ID_PD_P_APU_CORE04),
43 (SET_SCMI_CHANNEL_ID(0x0) | SCP_POWER_DOMAIN_ID_PD_P_APU_CORE05),
44 (SET_SCMI_CHANNEL_ID(0x0) | SCP_POWER_DOMAIN_ID_PD_P_APU_CORE06),
45 (SET_SCMI_CHANNEL_ID(0x0) | SCP_POWER_DOMAIN_ID_PD_P_APU_CORE07),
46 (SET_SCMI_CHANNEL_ID(0x0) | SCP_POWER_DOMAIN_ID_PD_P_APU_CORE08),
47 (SET_SCMI_CHANNEL_ID(0x0) | SCP_POWER_DOMAIN_ID_PD_P_APU_CORE09),
48 (SET_SCMI_CHANNEL_ID(0x0) | SCP_POWER_DOMAIN_ID_PD_P_APU_CORE10),
49 (SET_SCMI_CHANNEL_ID(0x0) | SCP_POWER_DOMAIN_ID_PD_P_APU_CORE11),
50 (SET_SCMI_CHANNEL_ID(0x0) | SCP_POWER_DOMAIN_ID_PD_P_APU_CORE12),
51 (SET_SCMI_CHANNEL_ID(0x0) | SCP_POWER_DOMAIN_ID_PD_P_APU_CORE13),
52 (SET_SCMI_CHANNEL_ID(0x0) | SCP_POWER_DOMAIN_ID_PD_P_APU_CORE14),
53 (SET_SCMI_CHANNEL_ID(0x0) | SCP_POWER_DOMAIN_ID_PD_P_APU_CORE15),
54 (SET_SCMI_CHANNEL_ID(0x0) | SCP_POWER_DOMAIN_ID_PD_P_APU_CORE16),
55 (SET_SCMI_CHANNEL_ID(0x0) | SCP_POWER_DOMAIN_ID_PD_P_APU_CORE17),
56 (SET_SCMI_CHANNEL_ID(0x0) | SCP_POWER_DOMAIN_ID_PD_P_APU_CORE18),
57 (SET_SCMI_CHANNEL_ID(0x0) | SCP_POWER_DOMAIN_ID_PD_P_APU_CORE19),
58 (SET_SCMI_CHANNEL_ID(0x0) | SCP_POWER_DOMAIN_ID_PD_P_APU_CORE20),
59 (SET_SCMI_CHANNEL_ID(0x0) | SCP_POWER_DOMAIN_ID_PD_P_APU_CORE21),
60 (SET_SCMI_CHANNEL_ID(0x0) | SCP_POWER_DOMAIN_ID_PD_P_APU_CORE22),
61 (SET_SCMI_CHANNEL_ID(0x0) | SCP_POWER_DOMAIN_ID_PD_P_APU_CORE23),
62 (SET_SCMI_CHANNEL_ID(0x0) | SCP_POWER_DOMAIN_ID_PD_P_APU_CORE24),
63 (SET_SCMI_CHANNEL_ID(0x0) | SCP_POWER_DOMAIN_ID_PD_P_APU_CORE25),
64 (SET_SCMI_CHANNEL_ID(0x0) | SCP_POWER_DOMAIN_ID_PD_P_APU_CORE26),
65 (SET_SCMI_CHANNEL_ID(0x0) | SCP_POWER_DOMAIN_ID_PD_P_APU_CORE27),
66 (SET_SCMI_CHANNEL_ID(0x0) | SCP_POWER_DOMAIN_ID_PD_P_APU_CORE28),
67 (SET_SCMI_CHANNEL_ID(0x0) | SCP_POWER_DOMAIN_ID_PD_P_APU_CORE29),
68 (SET_SCMI_CHANNEL_ID(0x0) | SCP_POWER_DOMAIN_ID_PD_P_APU_CORE30),
69 (SET_SCMI_CHANNEL_ID(0x0) | SCP_POWER_DOMAIN_ID_PD_P_APU_CORE31),
70 };
71
72
plat_core_pos_by_mpidr(u_register_t mpidr)73 int plat_core_pos_by_mpidr(u_register_t mpidr)
74 {
75 u_register_t cpu;
76
77 /* ARMv8.2 arch */
78 if ((mpidr & (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) != 0U) {
79 return -1;
80 }
81
82 cpu = plat_renesas_calc_core_pos(mpidr);
83 if (cpu >= PLATFORM_CORE_COUNT) {
84 return -1;
85 }
86
87 return (int)cpu;
88 }
89
rcar_cluster_pos_by_mpidr(u_register_t mpidr)90 int32_t rcar_cluster_pos_by_mpidr(u_register_t mpidr)
91 {
92 u_register_t cluster;
93
94 /* ARMv8.2 arch */
95 if ((mpidr & (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) != 0U) {
96 return -1;
97 }
98
99 cluster = MPIDR_AFFLVL2_VAL(mpidr);
100 if (cluster >= PLATFORM_CLUSTER_COUNT) {
101 return -1;
102 }
103
104 return (int32_t)cluster;
105 }
106
107 /* FIXME: Selective counter enablement is mandatory here ! */
108 uint16_t plat_amu_aux_enables[PLATFORM_CORE_COUNT] = {
109 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
110 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
111 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
112 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
113 };
114