1*dfd5bfb0SChandni Cherukuri/* 2*dfd5bfb0SChandni Cherukuri * Copyright (c) 2020, Arm Limited. All rights reserved. 3*dfd5bfb0SChandni Cherukuri * 4*dfd5bfb0SChandni Cherukuri * SPDX-License-Identifier: BSD-3-Clause 5*dfd5bfb0SChandni Cherukuri */ 6*dfd5bfb0SChandni Cherukuri 7*dfd5bfb0SChandni Cherukuri#include <arch.h> 8*dfd5bfb0SChandni Cherukuri#include <asm_macros.S> 9*dfd5bfb0SChandni Cherukuri#include <cpu_macros.S> 10*dfd5bfb0SChandni Cherukuri#include <rainier.h> 11*dfd5bfb0SChandni Cherukuri 12*dfd5bfb0SChandni Cherukuri#include <platform_def.h> 13*dfd5bfb0SChandni Cherukuri 14*dfd5bfb0SChandni Cherukuri .globl plat_arm_calc_core_pos 15*dfd5bfb0SChandni Cherukuri .globl plat_reset_handler 16*dfd5bfb0SChandni Cherukuri 17*dfd5bfb0SChandni Cherukuri /* ----------------------------------------------------- 18*dfd5bfb0SChandni Cherukuri * unsigned int plat_arm_calc_core_pos(u_register_t mpidr) 19*dfd5bfb0SChandni Cherukuri * 20*dfd5bfb0SChandni Cherukuri * Helper function to calculate the core position. 21*dfd5bfb0SChandni Cherukuri * ((ChipId * MORELLO_MAX_CLUSTERS_PER_CHIP + ClusterId) * 22*dfd5bfb0SChandni Cherukuri * MORELLO_MAX_CPUS_PER_CLUSTER * MORELLO_MAX_PE_PER_CPU) + 23*dfd5bfb0SChandni Cherukuri * (CPUId * MORELLO_MAX_PE_PER_CPU) + ThreadId 24*dfd5bfb0SChandni Cherukuri * 25*dfd5bfb0SChandni Cherukuri * which can be simplified as: 26*dfd5bfb0SChandni Cherukuri * 27*dfd5bfb0SChandni Cherukuri * (((ChipId * MORELLO_MAX_CLUSTERS_PER_CHIP + ClusterId) * 28*dfd5bfb0SChandni Cherukuri * MORELLO_MAX_CPUS_PER_CLUSTER + CPUId) * MORELLO_MAX_PE_PER_CPU) + 29*dfd5bfb0SChandni Cherukuri * ThreadId 30*dfd5bfb0SChandni Cherukuri * ------------------------------------------------------ 31*dfd5bfb0SChandni Cherukuri */ 32*dfd5bfb0SChandni Cherukuri 33*dfd5bfb0SChandni Cherukurifunc plat_arm_calc_core_pos 34*dfd5bfb0SChandni Cherukuri mov x4, x0 35*dfd5bfb0SChandni Cherukuri 36*dfd5bfb0SChandni Cherukuri /* 37*dfd5bfb0SChandni Cherukuri * The MT bit in MPIDR is always set for morello and the 38*dfd5bfb0SChandni Cherukuri * affinity level 0 corresponds to thread affinity level. 39*dfd5bfb0SChandni Cherukuri */ 40*dfd5bfb0SChandni Cherukuri 41*dfd5bfb0SChandni Cherukuri /* Extract individual affinity fields from MPIDR */ 42*dfd5bfb0SChandni Cherukuri ubfx x0, x4, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS 43*dfd5bfb0SChandni Cherukuri ubfx x1, x4, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS 44*dfd5bfb0SChandni Cherukuri ubfx x2, x4, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS 45*dfd5bfb0SChandni Cherukuri ubfx x3, x4, #MPIDR_AFF3_SHIFT, #MPIDR_AFFINITY_BITS 46*dfd5bfb0SChandni Cherukuri 47*dfd5bfb0SChandni Cherukuri /* Compute linear position */ 48*dfd5bfb0SChandni Cherukuri mov x4, #MORELLO_MAX_CLUSTERS_PER_CHIP 49*dfd5bfb0SChandni Cherukuri madd x2, x3, x4, x2 50*dfd5bfb0SChandni Cherukuri mov x4, #MORELLO_MAX_CPUS_PER_CLUSTER 51*dfd5bfb0SChandni Cherukuri madd x1, x2, x4, x1 52*dfd5bfb0SChandni Cherukuri mov x4, #MORELLO_MAX_PE_PER_CPU 53*dfd5bfb0SChandni Cherukuri madd x0, x1, x4, x0 54*dfd5bfb0SChandni Cherukuri ret 55*dfd5bfb0SChandni Cherukuriendfunc plat_arm_calc_core_pos 56