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Searched refs:uint32_t (Results 1 – 25 of 4103) sorted by relevance

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/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/
H A Dv10_structs.h29 uint32_t reserved_0; // offset: 0 (0x0)
30 uint32_t reserved_1; // offset: 1 (0x1)
31 uint32_t reserved_2; // offset: 2 (0x2)
32 uint32_t reserved_3; // offset: 3 (0x3)
33 uint32_t reserved_4; // offset: 4 (0x4)
34 uint32_t reserved_5; // offset: 5 (0x5)
35 uint32_t reserved_6; // offset: 6 (0x6)
36 uint32_t reserved_7; // offset: 7 (0x7)
37 uint32_t reserved_8; // offset: 8 (0x8)
38 uint32_t reserved_9; // offset: 9 (0x9)
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H A Dv9_structs.h28 uint32_t sdmax_rlcx_rb_cntl;
29 uint32_t sdmax_rlcx_rb_base;
30 uint32_t sdmax_rlcx_rb_base_hi;
31 uint32_t sdmax_rlcx_rb_rptr;
32 uint32_t sdmax_rlcx_rb_rptr_hi;
33 uint32_t sdmax_rlcx_rb_wptr;
34 uint32_t sdmax_rlcx_rb_wptr_hi;
35 uint32_t sdmax_rlcx_rb_wptr_poll_cntl;
36 uint32_t sdmax_rlcx_rb_rptr_addr_hi;
37 uint32_t sdmax_rlcx_rb_rptr_addr_lo;
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H A Dvi_structs.h28 uint32_t sdmax_rlcx_rb_cntl;
29 uint32_t sdmax_rlcx_rb_base;
30 uint32_t sdmax_rlcx_rb_base_hi;
31 uint32_t sdmax_rlcx_rb_rptr;
32 uint32_t sdmax_rlcx_rb_wptr;
33 uint32_t sdmax_rlcx_rb_wptr_poll_cntl;
34 uint32_t sdmax_rlcx_rb_wptr_poll_addr_hi;
35 uint32_t sdmax_rlcx_rb_wptr_poll_addr_lo;
36 uint32_t sdmax_rlcx_rb_rptr_addr_hi;
37 uint32_t sdmax_rlcx_rb_rptr_addr_lo;
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H A Dcik_structs.h28 uint32_t header;
29 uint32_t compute_dispatch_initiator;
30 uint32_t compute_dim_x;
31 uint32_t compute_dim_y;
32 uint32_t compute_dim_z;
33 uint32_t compute_start_x;
34 uint32_t compute_start_y;
35 uint32_t compute_start_z;
36 uint32_t compute_num_thread_x;
37 uint32_t compute_num_thread_y;
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/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dioc_rk3562.h12 uint32_t gpio1a_iomux_sel_l; /* Address Offset: 0x0000 */
13 uint32_t gpio1a_iomux_sel_h; /* Address Offset: 0x0004 */
14 uint32_t gpio1b_iomux_sel_l; /* Address Offset: 0x0008 */
15 uint32_t gpio1b_iomux_sel_h; /* Address Offset: 0x000C */
16 uint32_t gpio1c_iomux_sel_l; /* Address Offset: 0x0010 */
17 uint32_t gpio1c_iomux_sel_h; /* Address Offset: 0x0014 */
18 uint32_t gpio1d_iomux_sel_l; /* Address Offset: 0x0018 */
19 uint32_t gpio1d_iomux_sel_h; /* Address Offset: 0x001C */
20 uint32_t gpio2a_iomux_sel_l; /* Address Offset: 0x0020 */
21 uint32_t reserved0024[23]; /* Address Offset: 0x0024 */
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H A Dgrf_rk3588.h12 uint32_t wdt_con0; /* Address Offset: 0x0000 */
13 uint32_t reserved0004[3]; /* Address Offset: 0x0004 */
14 uint32_t uart_con0; /* Address Offset: 0x0010 */
15 uint32_t uart_con1; /* Address Offset: 0x0014 */
16 uint32_t reserved0018[42]; /* Address Offset: 0x0018 */
17 uint32_t gic_con0; /* Address Offset: 0x00C0 */
18 uint32_t reserved00c4[79]; /* Address Offset: 0x00C4 */
19 uint32_t memcfg_con0; /* Address Offset: 0x0200 */
20 uint32_t memcfg_con1; /* Address Offset: 0x0204 */
21 uint32_t memcfg_con2; /* Address Offset: 0x0208 */
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H A Dioc_rk3528.h12 uint32_t gpio0a_iomux_sel_l; /* Address Offset: 0x0000 */
13 uint32_t gpio0a_iomux_sel_h; /* Address Offset: 0x0004 */
14 uint32_t reserved0008[62]; /* Address Offset: 0x0008 */
15 uint32_t gpio0a_ds[3]; /* Address Offset: 0x0100 */
16 uint32_t reserved010c[61]; /* Address Offset: 0x010C */
17 uint32_t gpio0a_pull; /* Address Offset: 0x0200 */
18 uint32_t reserved0204[63]; /* Address Offset: 0x0204 */
19 uint32_t gpio0a_ie; /* Address Offset: 0x0300 */
20 uint32_t reserved0304[63]; /* Address Offset: 0x0304 */
21 uint32_t gpio0a_smt; /* Address Offset: 0x0400 */
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H A Dioc_rk3588.h12 uint32_t reserved0000[3]; /* Address Offset: 0x0000 */
13 uint32_t gpio0b_iomux_sel_h; /* Address Offset: 0x000C */
14 uint32_t gpio0c_iomux_sel_l; /* Address Offset: 0x0010 */
15 uint32_t gpio0c_iomux_sel_h; /* Address Offset: 0x0014 */
16 uint32_t gpio0d_iomux_sel_l; /* Address Offset: 0x0018 */
17 uint32_t gpio0d_iomux_sel_h; /* Address Offset: 0x001C */
18 uint32_t gpio1a_iomux_sel_l; /* Address Offset: 0x0020 */
19 uint32_t gpio1a_iomux_sel_h; /* Address Offset: 0x0024 */
20 uint32_t gpio1b_iomux_sel_l; /* Address Offset: 0x0028 */
21 uint32_t gpio1b_iomux_sel_h; /* Address Offset: 0x002C */
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/OK3568_Linux_fs/kernel/arch/mips/include/asm/octeon/
H A Dcvmx-pciercx-defs.h55 uint32_t u32;
57 __BITFIELD_FIELD(uint32_t dpe:1,
58 __BITFIELD_FIELD(uint32_t sse:1,
59 __BITFIELD_FIELD(uint32_t rma:1,
60 __BITFIELD_FIELD(uint32_t rta:1,
61 __BITFIELD_FIELD(uint32_t sta:1,
62 __BITFIELD_FIELD(uint32_t devt:2,
63 __BITFIELD_FIELD(uint32_t mdpe:1,
64 __BITFIELD_FIELD(uint32_t fbb:1,
65 __BITFIELD_FIELD(uint32_t reserved_22_22:1,
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/msm/disp/mdp5/
H A Dmdp5.xml.h180 static inline uint32_t MDSS_HW_VERSION_STEP(uint32_t val) in MDSS_HW_VERSION_STEP()
186 static inline uint32_t MDSS_HW_VERSION_MINOR(uint32_t val) in MDSS_HW_VERSION_MINOR()
192 static inline uint32_t MDSS_HW_VERSION_MAJOR(uint32_t val) in MDSS_HW_VERSION_MAJOR()
207 static inline uint32_t MDP5_HW_VERSION_STEP(uint32_t val) in MDP5_HW_VERSION_STEP()
213 static inline uint32_t MDP5_HW_VERSION_MINOR(uint32_t val) in MDP5_HW_VERSION_MINOR()
219 static inline uint32_t MDP5_HW_VERSION_MAJOR(uint32_t val) in MDP5_HW_VERSION_MAJOR()
227 static inline uint32_t MDP5_DISP_INTF_SEL_INTF0(enum mdp5_intf_type val) in MDP5_DISP_INTF_SEL_INTF0()
233 static inline uint32_t MDP5_DISP_INTF_SEL_INTF1(enum mdp5_intf_type val) in MDP5_DISP_INTF_SEL_INTF1()
239 static inline uint32_t MDP5_DISP_INTF_SEL_INTF2(enum mdp5_intf_type val) in MDP5_DISP_INTF_SEL_INTF2()
245 static inline uint32_t MDP5_DISP_INTF_SEL_INTF3(enum mdp5_intf_type val) in MDP5_DISP_INTF_SEL_INTF3()
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_pm4_headers_ai.h31 uint32_t reserved1 : 8; /* < reserved */
32 uint32_t opcode : 8; /* < IT opcode */
33 uint32_t count : 14;/* < number of DWORDs - 1 in the
36 uint32_t type : 2; /* < packet identifier.
40 uint32_t u32All;
58 uint32_t ordinal1;
63 uint32_t vmid_mask:16;
64 uint32_t unmap_latency:8;
65 uint32_t reserved1:5;
68 uint32_t ordinal2;
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H A Dkfd_pm4_headers_vi.h31 uint32_t reserved1 : 8; /* < reserved */
32 uint32_t opcode : 8; /* < IT opcode */
33 uint32_t count : 14;/* < Number of DWORDS - 1 in the
36 uint32_t type : 2; /* < packet identifier
40 uint32_t u32All;
58 uint32_t ordinal1;
63 uint32_t vmid_mask:16;
64 uint32_t unmap_latency:8;
65 uint32_t reserved1:5;
68 uint32_t ordinal2;
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/OK3568_Linux_fs/kernel/drivers/scsi/arcmsr/
H A Darcmsr.h98 #define dma_addr_hi32(addr) (uint32_t) ((addr>>16)>>16)
99 #define dma_addr_lo32(addr) (uint32_t) (addr & 0xffffffff)
107 uint32_t HeaderLength;
109 uint32_t Timeout;
110 uint32_t ControlCode;
111 uint32_t ReturnCode;
112 uint32_t Length;
190 uint32_t data_len;
200 uint32_t signature; /*0, 00-03*/
201 uint32_t request_len; /*1, 04-07*/
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/include/
H A Dgrph_object_ctrl_defs.h67 uint32_t enum_id:16; /* 1 based enum */
73 uint32_t clk_mask_register_index;
74 uint32_t clk_en_register_index;
75 uint32_t clk_y_register_index;
76 uint32_t clk_a_register_index;
77 uint32_t data_mask_register_index;
78 uint32_t data_en_register_index;
79 uint32_t data_y_register_index;
80 uint32_t data_a_register_index;
82 uint32_t clk_mask_shift;
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/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-ep93xx/
H A Dep93xx.h36 uint32_t control;
37 uint32_t interrupt;
38 uint32_t ppalloc;
39 uint32_t status;
40 uint32_t reserved0;
41 uint32_t remain;
42 uint32_t reserved1[2];
43 uint32_t maxcnt0;
44 uint32_t base0;
45 uint32_t current0;
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/msm/disp/mdp4/
H A Dmdp4.xml.h113 static inline uint32_t MDP4_VERSION_MINOR(uint32_t val) in MDP4_VERSION_MINOR()
119 static inline uint32_t MDP4_VERSION_MAJOR(uint32_t val) in MDP4_VERSION_MAJOR()
141 static inline uint32_t MDP4_DISP_INTF_SEL_PRIM(enum mdp4_intf val) in MDP4_DISP_INTF_SEL_PRIM()
147 static inline uint32_t MDP4_DISP_INTF_SEL_SEC(enum mdp4_intf val) in MDP4_DISP_INTF_SEL_SEC()
153 static inline uint32_t MDP4_DISP_INTF_SEL_EXT(enum mdp4_intf val) in MDP4_DISP_INTF_SEL_EXT()
183 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE0(enum mdp_mixer_stage_id val) in MDP4_LAYERMIXER2_IN_CFG_PIPE0()
190 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE1(enum mdp_mixer_stage_id val) in MDP4_LAYERMIXER2_IN_CFG_PIPE1()
197 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE2(enum mdp_mixer_stage_id val) in MDP4_LAYERMIXER2_IN_CFG_PIPE2()
204 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE3(enum mdp_mixer_stage_id val) in MDP4_LAYERMIXER2_IN_CFG_PIPE3()
211 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE4(enum mdp_mixer_stage_id val) in MDP4_LAYERMIXER2_IN_CFG_PIPE4()
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/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-mx7ulp/
H A Dimx_lpi2c.h92 #define LPI2C_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATUR…
95 #define LPI2C_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_…
98 #define LPI2C_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_…
103 #define LPI2C_PARAM_MTXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIF…
106 #define LPI2C_PARAM_MRXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIF…
111 #define LPI2C_MCR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIF…
114 #define LPI2C_MCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIF…
117 #define LPI2C_MCR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SH…
120 #define LPI2C_MCR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SH…
123 #define LPI2C_MCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIF…
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/OK3568_Linux_fs/kernel/drivers/scsi/lpfc/
H A Dlpfc_hw.h80 uint32_t Revision:8;
81 uint32_t InId:24;
83 uint32_t word;
89 uint32_t CmdRsp:16;
90 uint32_t Size:16;
92 uint32_t word;
115 uint32_t PortID;
134 uint32_t PortId; /* For RFT_ID requests */
137 uint32_t rsvd0:16;
138 uint32_t rsvd1:7;
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/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-mxs/
H A Dregs-digctl.h22 uint32_t hw_digctl_writeonce; /* 0x060 */
23 uint32_t reserved_writeonce[3];
26 uint32_t hw_digctl_entropy; /* 0x090 */
27 uint32_t reserved_entropy[3];
28 uint32_t hw_digctl_entropy_latched; /* 0x0a0 */
29 uint32_t reserved_entropy_latched[3];
31 uint32_t reserved1[4];
34 uint32_t hw_digctl_dbgrd; /* 0x0d0 */
35 uint32_t reserved_hw_digctl_dbgrd[3];
36 uint32_t hw_digctl_dbg; /* 0x0e0 */
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/OK3568_Linux_fs/external/security/librkcrypto/third_party/libdrm/include/
H A Dxf86drmMode.h75 uint32_t *fbs;
78 uint32_t *crtcs;
81 uint32_t *connectors;
84 uint32_t *encoders;
86 uint32_t min_width, max_width;
87 uint32_t min_height, max_height;
91 uint32_t clock;
95 uint32_t vrefresh;
97 uint32_t flags;
98 uint32_t type;
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/OK3568_Linux_fs/kernel/tools/firewire/
H A Dnosy-dump.h15 uint32_t timestamp;
18 uint32_t zero:24;
19 uint32_t phy_id:6;
20 uint32_t identifier:2;
24 uint32_t zero:16;
25 uint32_t gap_count:6;
26 uint32_t set_gap_count:1;
27 uint32_t set_root:1;
28 uint32_t root_id:6;
29 uint32_t identifier:2;
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/OK3568_Linux_fs/u-boot/drivers/net/
H A Dfec_mxc.h25 uint32_t res0[1]; /* MBAR_ETH + 0x000 */
26 uint32_t ievent; /* MBAR_ETH + 0x004 */
27 uint32_t imask; /* MBAR_ETH + 0x008 */
29 uint32_t res1[1]; /* MBAR_ETH + 0x00C */
30 uint32_t r_des_active; /* MBAR_ETH + 0x010 */
31 uint32_t x_des_active; /* MBAR_ETH + 0x014 */
32 uint32_t res2[3]; /* MBAR_ETH + 0x018-20 */
33 uint32_t ecntrl; /* MBAR_ETH + 0x024 */
35 uint32_t res3[6]; /* MBAR_ETH + 0x028-03C */
36 uint32_t mii_data; /* MBAR_ETH + 0x040 */
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_ucode.h29 uint32_t size_bytes; /* size of the entire header+image(s) in bytes */
30 uint32_t header_size_bytes; /* size of just the header in bytes */
35 uint32_t ucode_version;
36 uint32_t ucode_size_bytes; /* size of ucode in bytes */
37 uint32_t ucode_array_offset_bytes; /* payload offset from the start of the header */
38 uint32_t crc32; /* crc32 checksum of the payload */
44 uint32_t io_debug_size_bytes; /* size of debug array in dwords */
45 uint32_t io_debug_array_offset_bytes; /* payload offset from the start of the header */
51 uint32_t ucode_start_addr;
57 uint32_t ppt_offset_bytes; /* soft pptable offset */
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/meson/
H A Dmeson_drv.h63 uint32_t osd1_ctrl_stat;
64 uint32_t osd1_ctrl_stat2;
65 uint32_t osd1_blk0_cfg[5];
66 uint32_t osd1_blk1_cfg4;
67 uint32_t osd1_blk2_cfg4;
68 uint32_t osd1_addr;
69 uint32_t osd1_stride;
70 uint32_t osd1_height;
71 uint32_t osd1_width;
72 uint32_t osd_sc_ctrl0;
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/msm/adreno/
H A Da6xx.xml.h1021 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_RB_LO(uint32_t val) in A6XX_CP_ROQ_THRESHOLDS_1_RB_LO()
1027 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_RB_HI(uint32_t val) in A6XX_CP_ROQ_THRESHOLDS_1_RB_HI()
1033 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_IB1_START(uint32_t val) in A6XX_CP_ROQ_THRESHOLDS_1_IB1_START()
1039 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_IB2_START(uint32_t val) in A6XX_CP_ROQ_THRESHOLDS_1_IB2_START()
1047 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_2_SDS_START(uint32_t val) in A6XX_CP_ROQ_THRESHOLDS_2_SDS_START()
1053 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE(uint32_t val) in A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE()
1068 static inline uint32_t REG_A6XX_CP_SCRATCH(uint32_t i0) { return 0x00000883 + 0x1*i0; } in REG_A6XX_CP_SCRATCH()
1070 static inline uint32_t REG_A6XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000883 + 0x1*i0; } in REG_A6XX_CP_SCRATCH_REG()
1072 static inline uint32_t REG_A6XX_CP_PROTECT(uint32_t i0) { return 0x00000850 + 0x1*i0; } in REG_A6XX_CP_PROTECT()
1074 static inline uint32_t REG_A6XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000850 + 0x1*i0; } in REG_A6XX_CP_PROTECT_REG()
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