xref: /OK3568_Linux_fs/kernel/drivers/gpu/drm/meson/meson_drv.h (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (C) 2016 BayLibre, SAS
4*4882a593Smuzhiyun  * Author: Neil Armstrong <narmstrong@baylibre.com>
5*4882a593Smuzhiyun  */
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun #ifndef __MESON_DRV_H
8*4882a593Smuzhiyun #define __MESON_DRV_H
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun #include <linux/device.h>
11*4882a593Smuzhiyun #include <linux/of.h>
12*4882a593Smuzhiyun #include <linux/of_device.h>
13*4882a593Smuzhiyun #include <linux/regmap.h>
14*4882a593Smuzhiyun 
15*4882a593Smuzhiyun struct drm_crtc;
16*4882a593Smuzhiyun struct drm_device;
17*4882a593Smuzhiyun struct drm_plane;
18*4882a593Smuzhiyun struct meson_drm;
19*4882a593Smuzhiyun struct meson_afbcd_ops;
20*4882a593Smuzhiyun 
21*4882a593Smuzhiyun enum vpu_compatible {
22*4882a593Smuzhiyun 	VPU_COMPATIBLE_GXBB = 0,
23*4882a593Smuzhiyun 	VPU_COMPATIBLE_GXL  = 1,
24*4882a593Smuzhiyun 	VPU_COMPATIBLE_GXM  = 2,
25*4882a593Smuzhiyun 	VPU_COMPATIBLE_G12A = 3,
26*4882a593Smuzhiyun };
27*4882a593Smuzhiyun 
28*4882a593Smuzhiyun struct meson_drm_match_data {
29*4882a593Smuzhiyun 	enum vpu_compatible compat;
30*4882a593Smuzhiyun 	struct meson_afbcd_ops *afbcd_ops;
31*4882a593Smuzhiyun };
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun struct meson_drm_soc_limits {
34*4882a593Smuzhiyun 	unsigned int max_hdmi_phy_freq;
35*4882a593Smuzhiyun };
36*4882a593Smuzhiyun 
37*4882a593Smuzhiyun struct meson_drm {
38*4882a593Smuzhiyun 	struct device *dev;
39*4882a593Smuzhiyun 	enum vpu_compatible compat;
40*4882a593Smuzhiyun 	void __iomem *io_base;
41*4882a593Smuzhiyun 	struct regmap *hhi;
42*4882a593Smuzhiyun 	int vsync_irq;
43*4882a593Smuzhiyun 
44*4882a593Smuzhiyun 	struct meson_canvas *canvas;
45*4882a593Smuzhiyun 	u8 canvas_id_osd1;
46*4882a593Smuzhiyun 	u8 canvas_id_vd1_0;
47*4882a593Smuzhiyun 	u8 canvas_id_vd1_1;
48*4882a593Smuzhiyun 	u8 canvas_id_vd1_2;
49*4882a593Smuzhiyun 
50*4882a593Smuzhiyun 	struct drm_device *drm;
51*4882a593Smuzhiyun 	struct drm_crtc *crtc;
52*4882a593Smuzhiyun 	struct drm_plane *primary_plane;
53*4882a593Smuzhiyun 	struct drm_plane *overlay_plane;
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun 	const struct meson_drm_soc_limits *limits;
56*4882a593Smuzhiyun 
57*4882a593Smuzhiyun 	/* Components Data */
58*4882a593Smuzhiyun 	struct {
59*4882a593Smuzhiyun 		bool osd1_enabled;
60*4882a593Smuzhiyun 		bool osd1_interlace;
61*4882a593Smuzhiyun 		bool osd1_commit;
62*4882a593Smuzhiyun 		bool osd1_afbcd;
63*4882a593Smuzhiyun 		uint32_t osd1_ctrl_stat;
64*4882a593Smuzhiyun 		uint32_t osd1_ctrl_stat2;
65*4882a593Smuzhiyun 		uint32_t osd1_blk0_cfg[5];
66*4882a593Smuzhiyun 		uint32_t osd1_blk1_cfg4;
67*4882a593Smuzhiyun 		uint32_t osd1_blk2_cfg4;
68*4882a593Smuzhiyun 		uint32_t osd1_addr;
69*4882a593Smuzhiyun 		uint32_t osd1_stride;
70*4882a593Smuzhiyun 		uint32_t osd1_height;
71*4882a593Smuzhiyun 		uint32_t osd1_width;
72*4882a593Smuzhiyun 		uint32_t osd_sc_ctrl0;
73*4882a593Smuzhiyun 		uint32_t osd_sc_i_wh_m1;
74*4882a593Smuzhiyun 		uint32_t osd_sc_o_h_start_end;
75*4882a593Smuzhiyun 		uint32_t osd_sc_o_v_start_end;
76*4882a593Smuzhiyun 		uint32_t osd_sc_v_ini_phase;
77*4882a593Smuzhiyun 		uint32_t osd_sc_v_phase_step;
78*4882a593Smuzhiyun 		uint32_t osd_sc_h_ini_phase;
79*4882a593Smuzhiyun 		uint32_t osd_sc_h_phase_step;
80*4882a593Smuzhiyun 		uint32_t osd_sc_h_ctrl0;
81*4882a593Smuzhiyun 		uint32_t osd_sc_v_ctrl0;
82*4882a593Smuzhiyun 		uint32_t osd_blend_din0_scope_h;
83*4882a593Smuzhiyun 		uint32_t osd_blend_din0_scope_v;
84*4882a593Smuzhiyun 		uint32_t osb_blend0_size;
85*4882a593Smuzhiyun 		uint32_t osb_blend1_size;
86*4882a593Smuzhiyun 
87*4882a593Smuzhiyun 		bool vd1_enabled;
88*4882a593Smuzhiyun 		bool vd1_commit;
89*4882a593Smuzhiyun 		bool vd1_afbc;
90*4882a593Smuzhiyun 		unsigned int vd1_planes;
91*4882a593Smuzhiyun 		uint32_t vd1_if0_gen_reg;
92*4882a593Smuzhiyun 		uint32_t vd1_if0_luma_x0;
93*4882a593Smuzhiyun 		uint32_t vd1_if0_luma_y0;
94*4882a593Smuzhiyun 		uint32_t vd1_if0_chroma_x0;
95*4882a593Smuzhiyun 		uint32_t vd1_if0_chroma_y0;
96*4882a593Smuzhiyun 		uint32_t vd1_if0_repeat_loop;
97*4882a593Smuzhiyun 		uint32_t vd1_if0_luma0_rpt_pat;
98*4882a593Smuzhiyun 		uint32_t vd1_if0_chroma0_rpt_pat;
99*4882a593Smuzhiyun 		uint32_t vd1_range_map_y;
100*4882a593Smuzhiyun 		uint32_t vd1_range_map_cb;
101*4882a593Smuzhiyun 		uint32_t vd1_range_map_cr;
102*4882a593Smuzhiyun 		uint32_t viu_vd1_fmt_w;
103*4882a593Smuzhiyun 		uint32_t vd1_if0_canvas0;
104*4882a593Smuzhiyun 		uint32_t vd1_if0_gen_reg2;
105*4882a593Smuzhiyun 		uint32_t viu_vd1_fmt_ctrl;
106*4882a593Smuzhiyun 		uint32_t vd1_addr0;
107*4882a593Smuzhiyun 		uint32_t vd1_addr1;
108*4882a593Smuzhiyun 		uint32_t vd1_addr2;
109*4882a593Smuzhiyun 		uint32_t vd1_stride0;
110*4882a593Smuzhiyun 		uint32_t vd1_stride1;
111*4882a593Smuzhiyun 		uint32_t vd1_stride2;
112*4882a593Smuzhiyun 		uint32_t vd1_height0;
113*4882a593Smuzhiyun 		uint32_t vd1_height1;
114*4882a593Smuzhiyun 		uint32_t vd1_height2;
115*4882a593Smuzhiyun 		uint32_t vd1_afbc_mode;
116*4882a593Smuzhiyun 		uint32_t vd1_afbc_en;
117*4882a593Smuzhiyun 		uint32_t vd1_afbc_head_addr;
118*4882a593Smuzhiyun 		uint32_t vd1_afbc_body_addr;
119*4882a593Smuzhiyun 		uint32_t vd1_afbc_conv_ctrl;
120*4882a593Smuzhiyun 		uint32_t vd1_afbc_dec_def_color;
121*4882a593Smuzhiyun 		uint32_t vd1_afbc_vd_cfmt_ctrl;
122*4882a593Smuzhiyun 		uint32_t vd1_afbc_vd_cfmt_w;
123*4882a593Smuzhiyun 		uint32_t vd1_afbc_vd_cfmt_h;
124*4882a593Smuzhiyun 		uint32_t vd1_afbc_mif_hor_scope;
125*4882a593Smuzhiyun 		uint32_t vd1_afbc_mif_ver_scope;
126*4882a593Smuzhiyun 		uint32_t vd1_afbc_size_out;
127*4882a593Smuzhiyun 		uint32_t vd1_afbc_pixel_hor_scope;
128*4882a593Smuzhiyun 		uint32_t vd1_afbc_pixel_ver_scope;
129*4882a593Smuzhiyun 		uint32_t vd1_afbc_size_in;
130*4882a593Smuzhiyun 		uint32_t vpp_pic_in_height;
131*4882a593Smuzhiyun 		uint32_t vpp_postblend_vd1_h_start_end;
132*4882a593Smuzhiyun 		uint32_t vpp_postblend_vd1_v_start_end;
133*4882a593Smuzhiyun 		uint32_t vpp_hsc_region12_startp;
134*4882a593Smuzhiyun 		uint32_t vpp_hsc_region34_startp;
135*4882a593Smuzhiyun 		uint32_t vpp_hsc_region4_endp;
136*4882a593Smuzhiyun 		uint32_t vpp_hsc_start_phase_step;
137*4882a593Smuzhiyun 		uint32_t vpp_hsc_region1_phase_slope;
138*4882a593Smuzhiyun 		uint32_t vpp_hsc_region3_phase_slope;
139*4882a593Smuzhiyun 		uint32_t vpp_line_in_length;
140*4882a593Smuzhiyun 		uint32_t vpp_preblend_h_size;
141*4882a593Smuzhiyun 		uint32_t vpp_vsc_region12_startp;
142*4882a593Smuzhiyun 		uint32_t vpp_vsc_region34_startp;
143*4882a593Smuzhiyun 		uint32_t vpp_vsc_region4_endp;
144*4882a593Smuzhiyun 		uint32_t vpp_vsc_start_phase_step;
145*4882a593Smuzhiyun 		uint32_t vpp_vsc_ini_phase;
146*4882a593Smuzhiyun 		uint32_t vpp_vsc_phase_ctrl;
147*4882a593Smuzhiyun 		uint32_t vpp_hsc_phase_ctrl;
148*4882a593Smuzhiyun 		uint32_t vpp_blend_vd2_h_start_end;
149*4882a593Smuzhiyun 		uint32_t vpp_blend_vd2_v_start_end;
150*4882a593Smuzhiyun 	} viu;
151*4882a593Smuzhiyun 
152*4882a593Smuzhiyun 	struct {
153*4882a593Smuzhiyun 		unsigned int current_mode;
154*4882a593Smuzhiyun 		bool hdmi_repeat;
155*4882a593Smuzhiyun 		bool venc_repeat;
156*4882a593Smuzhiyun 		bool hdmi_use_enci;
157*4882a593Smuzhiyun 	} venc;
158*4882a593Smuzhiyun 
159*4882a593Smuzhiyun 	struct {
160*4882a593Smuzhiyun 		dma_addr_t addr_dma;
161*4882a593Smuzhiyun 		uint32_t *addr;
162*4882a593Smuzhiyun 		unsigned int offset;
163*4882a593Smuzhiyun 	} rdma;
164*4882a593Smuzhiyun 
165*4882a593Smuzhiyun 	struct {
166*4882a593Smuzhiyun 		struct meson_afbcd_ops *ops;
167*4882a593Smuzhiyun 		u64 modifier;
168*4882a593Smuzhiyun 		u32 format;
169*4882a593Smuzhiyun 	} afbcd;
170*4882a593Smuzhiyun };
171*4882a593Smuzhiyun 
meson_vpu_is_compatible(struct meson_drm * priv,enum vpu_compatible family)172*4882a593Smuzhiyun static inline int meson_vpu_is_compatible(struct meson_drm *priv,
173*4882a593Smuzhiyun 					  enum vpu_compatible family)
174*4882a593Smuzhiyun {
175*4882a593Smuzhiyun 	return priv->compat == family;
176*4882a593Smuzhiyun }
177*4882a593Smuzhiyun 
178*4882a593Smuzhiyun #endif /* __MESON_DRV_H */
179