1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2022 Rockchip Electronics Co., Ltd. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun #ifndef _ASM_ARCH_IOC_RK3562_H 7*4882a593Smuzhiyun #define _ASM_ARCH_IOC_RK3562_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <common.h> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun struct rk3562_ioc { 12*4882a593Smuzhiyun uint32_t gpio1a_iomux_sel_l; /* Address Offset: 0x0000 */ 13*4882a593Smuzhiyun uint32_t gpio1a_iomux_sel_h; /* Address Offset: 0x0004 */ 14*4882a593Smuzhiyun uint32_t gpio1b_iomux_sel_l; /* Address Offset: 0x0008 */ 15*4882a593Smuzhiyun uint32_t gpio1b_iomux_sel_h; /* Address Offset: 0x000C */ 16*4882a593Smuzhiyun uint32_t gpio1c_iomux_sel_l; /* Address Offset: 0x0010 */ 17*4882a593Smuzhiyun uint32_t gpio1c_iomux_sel_h; /* Address Offset: 0x0014 */ 18*4882a593Smuzhiyun uint32_t gpio1d_iomux_sel_l; /* Address Offset: 0x0018 */ 19*4882a593Smuzhiyun uint32_t gpio1d_iomux_sel_h; /* Address Offset: 0x001C */ 20*4882a593Smuzhiyun uint32_t gpio2a_iomux_sel_l; /* Address Offset: 0x0020 */ 21*4882a593Smuzhiyun uint32_t reserved0024[23]; /* Address Offset: 0x0024 */ 22*4882a593Smuzhiyun uint32_t gpio1a_p; /* Address Offset: 0x0080 */ 23*4882a593Smuzhiyun uint32_t gpio1b_p; /* Address Offset: 0x0084 */ 24*4882a593Smuzhiyun uint32_t gpio1c_p; /* Address Offset: 0x0088 */ 25*4882a593Smuzhiyun uint32_t gpio1d_p; /* Address Offset: 0x008C */ 26*4882a593Smuzhiyun uint32_t gpio2a_p; /* Address Offset: 0x0090 */ 27*4882a593Smuzhiyun uint32_t reserved0094[11]; /* Address Offset: 0x0094 */ 28*4882a593Smuzhiyun uint32_t gpio1a_ie; /* Address Offset: 0x00C0 */ 29*4882a593Smuzhiyun uint32_t gpio1b_ie; /* Address Offset: 0x00C4 */ 30*4882a593Smuzhiyun uint32_t gpio1c_ie; /* Address Offset: 0x00C8 */ 31*4882a593Smuzhiyun uint32_t gpio1d_ie; /* Address Offset: 0x00CC */ 32*4882a593Smuzhiyun uint32_t gpio2a_ie; /* Address Offset: 0x00D0 */ 33*4882a593Smuzhiyun uint32_t reserved00d4[11]; /* Address Offset: 0x00D4 */ 34*4882a593Smuzhiyun uint32_t gpio1a_od; /* Address Offset: 0x0100 */ 35*4882a593Smuzhiyun uint32_t gpio1b_od; /* Address Offset: 0x0104 */ 36*4882a593Smuzhiyun uint32_t gpio1c_od; /* Address Offset: 0x0108 */ 37*4882a593Smuzhiyun uint32_t gpio1d_od; /* Address Offset: 0x010C */ 38*4882a593Smuzhiyun uint32_t gpio2a_od; /* Address Offset: 0x0110 */ 39*4882a593Smuzhiyun uint32_t reserved0114[11]; /* Address Offset: 0x0114 */ 40*4882a593Smuzhiyun uint32_t gpio1a_sus; /* Address Offset: 0x0140 */ 41*4882a593Smuzhiyun uint32_t gpio1b_sus; /* Address Offset: 0x0144 */ 42*4882a593Smuzhiyun uint32_t gpio1c_sus; /* Address Offset: 0x0148 */ 43*4882a593Smuzhiyun uint32_t gpio1d_sus; /* Address Offset: 0x014C */ 44*4882a593Smuzhiyun uint32_t gpio2a_sus; /* Address Offset: 0x0150 */ 45*4882a593Smuzhiyun uint32_t reserved0154[11]; /* Address Offset: 0x0154 */ 46*4882a593Smuzhiyun uint32_t gpio1a_sl; /* Address Offset: 0x0180 */ 47*4882a593Smuzhiyun uint32_t gpio1b_sl; /* Address Offset: 0x0184 */ 48*4882a593Smuzhiyun uint32_t gpio1c_sl; /* Address Offset: 0x0188 */ 49*4882a593Smuzhiyun uint32_t gpio1d_sl; /* Address Offset: 0x018C */ 50*4882a593Smuzhiyun uint32_t gpio2a_sl; /* Address Offset: 0x0190 */ 51*4882a593Smuzhiyun uint32_t reserved0194[27]; /* Address Offset: 0x0194 */ 52*4882a593Smuzhiyun uint32_t gpio1a_ds0; /* Address Offset: 0x0200 */ 53*4882a593Smuzhiyun uint32_t gpio1a_ds1; /* Address Offset: 0x0204 */ 54*4882a593Smuzhiyun uint32_t gpio1a_ds2; /* Address Offset: 0x0208 */ 55*4882a593Smuzhiyun uint32_t gpio1a_ds3; /* Address Offset: 0x020C */ 56*4882a593Smuzhiyun uint32_t gpio1b_ds0; /* Address Offset: 0x0210 */ 57*4882a593Smuzhiyun uint32_t gpio1b_ds1; /* Address Offset: 0x0214 */ 58*4882a593Smuzhiyun uint32_t gpio1b_ds2; /* Address Offset: 0x0218 */ 59*4882a593Smuzhiyun uint32_t gpio1b_ds3; /* Address Offset: 0x021C */ 60*4882a593Smuzhiyun uint32_t gpio1c_ds0; /* Address Offset: 0x0220 */ 61*4882a593Smuzhiyun uint32_t gpio1c_ds1; /* Address Offset: 0x0224 */ 62*4882a593Smuzhiyun uint32_t gpio1c_ds2; /* Address Offset: 0x0228 */ 63*4882a593Smuzhiyun uint32_t gpio1c_ds3; /* Address Offset: 0x022C */ 64*4882a593Smuzhiyun uint32_t gpio1d_ds0; /* Address Offset: 0x0230 */ 65*4882a593Smuzhiyun uint32_t gpio1d_ds1; /* Address Offset: 0x0234 */ 66*4882a593Smuzhiyun uint32_t gpio1d_ds2; /* Address Offset: 0x0238 */ 67*4882a593Smuzhiyun uint32_t gpio1d_ds3; /* Address Offset: 0x023C */ 68*4882a593Smuzhiyun uint32_t gpio2a_ds0; /* Address Offset: 0x0240 */ 69*4882a593Smuzhiyun uint32_t reserved0244[47]; /* Address Offset: 0x0244 */ 70*4882a593Smuzhiyun uint32_t io_vsel0; /* Address Offset: 0x0300 */ 71*4882a593Smuzhiyun uint32_t reserved0304[63]; /* Address Offset: 0x0304 */ 72*4882a593Smuzhiyun uint32_t mac1_io_con0; /* Address Offset: 0x0400 */ 73*4882a593Smuzhiyun uint32_t mac1_io_con1; /* Address Offset: 0x0404 */ 74*4882a593Smuzhiyun uint32_t reserved0408[62]; /* Address Offset: 0x0408 */ 75*4882a593Smuzhiyun uint32_t sdcard0_io_con; /* Address Offset: 0x0500 */ 76*4882a593Smuzhiyun uint32_t jtag_m1_con; /* Address Offset: 0x0504 */ 77*4882a593Smuzhiyun uint32_t reserved0508[16078]; /* Address Offset: 0x0508 */ 78*4882a593Smuzhiyun uint32_t gpio3a_iomux_sel_l; /* Address Offset: 0x10040 */ 79*4882a593Smuzhiyun uint32_t gpio3a_iomux_sel_h; /* Address Offset: 0x10044 */ 80*4882a593Smuzhiyun uint32_t gpio3b_iomux_sel_l; /* Address Offset: 0x10048 */ 81*4882a593Smuzhiyun uint32_t gpio3b_iomux_sel_h; /* Address Offset: 0x1004C */ 82*4882a593Smuzhiyun uint32_t gpio3c_iomux_sel_l; /* Address Offset: 0x10050 */ 83*4882a593Smuzhiyun uint32_t gpio3c_iomux_sel_h; /* Address Offset: 0x10054 */ 84*4882a593Smuzhiyun uint32_t gpio3d_iomux_sel_l; /* Address Offset: 0x10058 */ 85*4882a593Smuzhiyun uint32_t gpio3d_iomux_sel_h; /* Address Offset: 0x1005C */ 86*4882a593Smuzhiyun uint32_t gpio4a_iomux_sel_l; /* Address Offset: 0x10060 */ 87*4882a593Smuzhiyun uint32_t gpio4a_iomux_sel_h; /* Address Offset: 0x10064 */ 88*4882a593Smuzhiyun uint32_t gpio4b_iomux_sel_l; /* Address Offset: 0x10068 */ 89*4882a593Smuzhiyun uint32_t gpio4b_iomux_sel_h; /* Address Offset: 0x1006C */ 90*4882a593Smuzhiyun uint32_t reserved10070[12]; /* Address Offset: 0x10070 */ 91*4882a593Smuzhiyun uint32_t gpio3a_p; /* Address Offset: 0x100A0 */ 92*4882a593Smuzhiyun uint32_t gpio3b_p; /* Address Offset: 0x100A4 */ 93*4882a593Smuzhiyun uint32_t gpio3c_p; /* Address Offset: 0x100A8 */ 94*4882a593Smuzhiyun uint32_t gpio3d_p; /* Address Offset: 0x100AC */ 95*4882a593Smuzhiyun uint32_t gpio4a_p; /* Address Offset: 0x100B0 */ 96*4882a593Smuzhiyun uint32_t gpio4b_p; /* Address Offset: 0x100B4 */ 97*4882a593Smuzhiyun uint32_t reserved100b8[10]; /* Address Offset: 0x100B8 */ 98*4882a593Smuzhiyun uint32_t gpio3a_ie; /* Address Offset: 0x100E0 */ 99*4882a593Smuzhiyun uint32_t gpio3b_ie; /* Address Offset: 0x100E4 */ 100*4882a593Smuzhiyun uint32_t gpio3c_ie; /* Address Offset: 0x100E8 */ 101*4882a593Smuzhiyun uint32_t gpio3d_ie; /* Address Offset: 0x100EC */ 102*4882a593Smuzhiyun uint32_t gpio4a_ie; /* Address Offset: 0x100F0 */ 103*4882a593Smuzhiyun uint32_t gpio4b_ie; /* Address Offset: 0x100F4 */ 104*4882a593Smuzhiyun uint32_t reserved100f8[10]; /* Address Offset: 0x100F8 */ 105*4882a593Smuzhiyun uint32_t gpio3a_od; /* Address Offset: 0x10120 */ 106*4882a593Smuzhiyun uint32_t gpio3b_od; /* Address Offset: 0x10124 */ 107*4882a593Smuzhiyun uint32_t gpio3c_od; /* Address Offset: 0x10128 */ 108*4882a593Smuzhiyun uint32_t gpio3d_od; /* Address Offset: 0x1012C */ 109*4882a593Smuzhiyun uint32_t gpio4a_od; /* Address Offset: 0x10130 */ 110*4882a593Smuzhiyun uint32_t gpio4b_od; /* Address Offset: 0x10134 */ 111*4882a593Smuzhiyun uint32_t reserved10138[10]; /* Address Offset: 0x10138 */ 112*4882a593Smuzhiyun uint32_t gpio3a_sus; /* Address Offset: 0x10160 */ 113*4882a593Smuzhiyun uint32_t gpio3b_sus; /* Address Offset: 0x10164 */ 114*4882a593Smuzhiyun uint32_t gpio3c_sus; /* Address Offset: 0x10168 */ 115*4882a593Smuzhiyun uint32_t gpio3d_sus; /* Address Offset: 0x1016C */ 116*4882a593Smuzhiyun uint32_t gpio4a_sus; /* Address Offset: 0x10170 */ 117*4882a593Smuzhiyun uint32_t gpio4b_sus; /* Address Offset: 0x10174 */ 118*4882a593Smuzhiyun uint32_t reserved10178[10]; /* Address Offset: 0x10178 */ 119*4882a593Smuzhiyun uint32_t gpio3a_sl; /* Address Offset: 0x101A0 */ 120*4882a593Smuzhiyun uint32_t gpio3b_sl; /* Address Offset: 0x101A4 */ 121*4882a593Smuzhiyun uint32_t gpio3c_sl; /* Address Offset: 0x101A8 */ 122*4882a593Smuzhiyun uint32_t gpio3d_sl; /* Address Offset: 0x101AC */ 123*4882a593Smuzhiyun uint32_t gpio4a_sl; /* Address Offset: 0x101B0 */ 124*4882a593Smuzhiyun uint32_t gpio4b_sl; /* Address Offset: 0x101B4 */ 125*4882a593Smuzhiyun uint32_t reserved101b8[50]; /* Address Offset: 0x101B8 */ 126*4882a593Smuzhiyun uint32_t gpio3a_ds0; /* Address Offset: 0x10280 */ 127*4882a593Smuzhiyun uint32_t gpio3a_ds1; /* Address Offset: 0x10284 */ 128*4882a593Smuzhiyun uint32_t gpio3a_ds2; /* Address Offset: 0x10288 */ 129*4882a593Smuzhiyun uint32_t gpio3a_ds3; /* Address Offset: 0x1028C */ 130*4882a593Smuzhiyun uint32_t gpio3b_ds0; /* Address Offset: 0x10290 */ 131*4882a593Smuzhiyun uint32_t gpio3b_ds1; /* Address Offset: 0x10294 */ 132*4882a593Smuzhiyun uint32_t gpio3b_ds2; /* Address Offset: 0x10298 */ 133*4882a593Smuzhiyun uint32_t gpio3b_ds3; /* Address Offset: 0x1029C */ 134*4882a593Smuzhiyun uint32_t gpio3c_ds0; /* Address Offset: 0x102A0 */ 135*4882a593Smuzhiyun uint32_t gpio3c_ds1; /* Address Offset: 0x102A4 */ 136*4882a593Smuzhiyun uint32_t gpio3c_ds2; /* Address Offset: 0x102A8 */ 137*4882a593Smuzhiyun uint32_t gpio3c_ds3; /* Address Offset: 0x102AC */ 138*4882a593Smuzhiyun uint32_t gpio3d_ds0; /* Address Offset: 0x102B0 */ 139*4882a593Smuzhiyun uint32_t gpio3d_ds1; /* Address Offset: 0x102B4 */ 140*4882a593Smuzhiyun uint32_t gpio3d_ds2; /* Address Offset: 0x102B8 */ 141*4882a593Smuzhiyun uint32_t gpio3d_ds3; /* Address Offset: 0x102BC */ 142*4882a593Smuzhiyun uint32_t gpio4a_ds0; /* Address Offset: 0x102C0 */ 143*4882a593Smuzhiyun uint32_t gpio4a_ds1; /* Address Offset: 0x102C4 */ 144*4882a593Smuzhiyun uint32_t gpio4a_ds2; /* Address Offset: 0x102C8 */ 145*4882a593Smuzhiyun uint32_t gpio4a_ds3; /* Address Offset: 0x102CC */ 146*4882a593Smuzhiyun uint32_t gpio4b_ds0; /* Address Offset: 0x102D0 */ 147*4882a593Smuzhiyun uint32_t gpio4b_ds1; /* Address Offset: 0x102D4 */ 148*4882a593Smuzhiyun uint32_t gpio4b_ds2; /* Address Offset: 0x102D8 */ 149*4882a593Smuzhiyun uint32_t gpio4b_ds3; /* Address Offset: 0x102DC */ 150*4882a593Smuzhiyun uint32_t reserved102e0[8]; /* Address Offset: 0x102E0 */ 151*4882a593Smuzhiyun uint32_t io_vsel1; /* Address Offset: 0x10300 */ 152*4882a593Smuzhiyun uint32_t reserved10304[63]; /* Address Offset: 0x10304 */ 153*4882a593Smuzhiyun uint32_t mac0_io_con0; /* Address Offset: 0x10400 */ 154*4882a593Smuzhiyun uint32_t mac0_io_con1; /* Address Offset: 0x10404 */ 155*4882a593Smuzhiyun uint32_t reserved10408[62]; /* Address Offset: 0x10408 */ 156*4882a593Smuzhiyun uint32_t vo_io_con; /* Address Offset: 0x10500 */ 157*4882a593Smuzhiyun uint32_t reserved10504[35]; /* Address Offset: 0x10504 */ 158*4882a593Smuzhiyun uint32_t saradc1_con; /* Address Offset: 0x10590 */ 159*4882a593Smuzhiyun uint32_t reserved10594[16027]; /* Address Offset: 0x10594 */ 160*4882a593Smuzhiyun uint32_t gpio0a_iomux_sel_l; /* Address Offset: 0x20000 */ 161*4882a593Smuzhiyun uint32_t gpio0a_iomux_sel_h; /* Address Offset: 0x20004 */ 162*4882a593Smuzhiyun uint32_t gpio0b_iomux_sel_l; /* Address Offset: 0x20008 */ 163*4882a593Smuzhiyun uint32_t gpio0b_iomux_sel_h; /* Address Offset: 0x2000C */ 164*4882a593Smuzhiyun uint32_t gpio0c_iomux_sel_l; /* Address Offset: 0x20010 */ 165*4882a593Smuzhiyun uint32_t gpio0c_iomux_sel_h; /* Address Offset: 0x20014 */ 166*4882a593Smuzhiyun uint32_t gpio0d_iomux_sel_l; /* Address Offset: 0x20018 */ 167*4882a593Smuzhiyun uint32_t reserved2001c; /* Address Offset: 0x2001C */ 168*4882a593Smuzhiyun uint32_t gpio0a_p; /* Address Offset: 0x20020 */ 169*4882a593Smuzhiyun uint32_t gpio0b_p; /* Address Offset: 0x20024 */ 170*4882a593Smuzhiyun uint32_t gpio0c_p; /* Address Offset: 0x20028 */ 171*4882a593Smuzhiyun uint32_t gpio0d_p; /* Address Offset: 0x2002C */ 172*4882a593Smuzhiyun uint32_t gpio0a_ie; /* Address Offset: 0x20030 */ 173*4882a593Smuzhiyun uint32_t gpio0b_ie; /* Address Offset: 0x20034 */ 174*4882a593Smuzhiyun uint32_t gpio0c_ie; /* Address Offset: 0x20038 */ 175*4882a593Smuzhiyun uint32_t gpio0d_ie; /* Address Offset: 0x2003C */ 176*4882a593Smuzhiyun uint32_t gpio0a_od; /* Address Offset: 0x20040 */ 177*4882a593Smuzhiyun uint32_t gpio0b_od; /* Address Offset: 0x20044 */ 178*4882a593Smuzhiyun uint32_t gpio0c_od; /* Address Offset: 0x20048 */ 179*4882a593Smuzhiyun uint32_t gpio0d_od; /* Address Offset: 0x2004C */ 180*4882a593Smuzhiyun uint32_t gpio0a_sus; /* Address Offset: 0x20050 */ 181*4882a593Smuzhiyun uint32_t gpio0b_sus; /* Address Offset: 0x20054 */ 182*4882a593Smuzhiyun uint32_t gpio0c_sus; /* Address Offset: 0x20058 */ 183*4882a593Smuzhiyun uint32_t gpio0d_sus; /* Address Offset: 0x2005C */ 184*4882a593Smuzhiyun uint32_t gpio0a_sl; /* Address Offset: 0x20060 */ 185*4882a593Smuzhiyun uint32_t gpio0b_sl; /* Address Offset: 0x20064 */ 186*4882a593Smuzhiyun uint32_t gpio0c_sl; /* Address Offset: 0x20068 */ 187*4882a593Smuzhiyun uint32_t gpio0d_sl; /* Address Offset: 0x2006C */ 188*4882a593Smuzhiyun uint32_t gpio0a_ds0; /* Address Offset: 0x20070 */ 189*4882a593Smuzhiyun uint32_t gpio0a_ds1; /* Address Offset: 0x20074 */ 190*4882a593Smuzhiyun uint32_t gpio0a_ds2; /* Address Offset: 0x20078 */ 191*4882a593Smuzhiyun uint32_t gpio0a_ds3; /* Address Offset: 0x2007C */ 192*4882a593Smuzhiyun uint32_t gpio0b_ds0; /* Address Offset: 0x20080 */ 193*4882a593Smuzhiyun uint32_t gpio0b_ds1; /* Address Offset: 0x20084 */ 194*4882a593Smuzhiyun uint32_t gpio0b_ds2; /* Address Offset: 0x20088 */ 195*4882a593Smuzhiyun uint32_t gpio0b_ds3; /* Address Offset: 0x2008C */ 196*4882a593Smuzhiyun uint32_t gpio0c_ds0; /* Address Offset: 0x20090 */ 197*4882a593Smuzhiyun uint32_t gpio0c_ds1; /* Address Offset: 0x20094 */ 198*4882a593Smuzhiyun uint32_t gpio0c_ds2; /* Address Offset: 0x20098 */ 199*4882a593Smuzhiyun uint32_t gpio0c_ds3; /* Address Offset: 0x2009C */ 200*4882a593Smuzhiyun uint32_t gpio0d_ds0; /* Address Offset: 0x200A0 */ 201*4882a593Smuzhiyun uint32_t reserved200a4[23]; /* Address Offset: 0x200A4 */ 202*4882a593Smuzhiyun uint32_t jtag_m0_con; /* Address Offset: 0x20100 */ 203*4882a593Smuzhiyun uint32_t uart_io_con; /* Address Offset: 0x20104 */ 204*4882a593Smuzhiyun uint32_t reserved20108[16]; /* Address Offset: 0x20108 */ 205*4882a593Smuzhiyun uint32_t io_vsel2; /* Address Offset: 0x20148 */ 206*4882a593Smuzhiyun uint32_t xin_con; /* Address Offset: 0x2014C */ 207*4882a593Smuzhiyun }; 208*4882a593Smuzhiyun check_member(rk3562_ioc, xin_con, 0x2014c); 209*4882a593Smuzhiyun 210*4882a593Smuzhiyun #endif 211*4882a593Smuzhiyun 212