1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Freescale i.MX28 DIGCTL Register Definitions 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2012 Robert Delien <robert@delien.nl> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __MX28_REGS_DIGCTL_H__ 10*4882a593Smuzhiyun #define __MX28_REGS_DIGCTL_H__ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include <asm/mach-imx/regs-common.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 15*4882a593Smuzhiyun struct mxs_digctl_regs { 16*4882a593Smuzhiyun mxs_reg_32(hw_digctl_ctrl) /* 0x000 */ 17*4882a593Smuzhiyun mxs_reg_32(hw_digctl_status) /* 0x010 */ 18*4882a593Smuzhiyun mxs_reg_32(hw_digctl_hclkcount) /* 0x020 */ 19*4882a593Smuzhiyun mxs_reg_32(hw_digctl_ramctrl) /* 0x030 */ 20*4882a593Smuzhiyun mxs_reg_32(hw_digctl_emi_status) /* 0x040 */ 21*4882a593Smuzhiyun mxs_reg_32(hw_digctl_read_margin) /* 0x050 */ 22*4882a593Smuzhiyun uint32_t hw_digctl_writeonce; /* 0x060 */ 23*4882a593Smuzhiyun uint32_t reserved_writeonce[3]; 24*4882a593Smuzhiyun mxs_reg_32(hw_digctl_bist_ctl) /* 0x070 */ 25*4882a593Smuzhiyun mxs_reg_32(hw_digctl_bist_status) /* 0x080 */ 26*4882a593Smuzhiyun uint32_t hw_digctl_entropy; /* 0x090 */ 27*4882a593Smuzhiyun uint32_t reserved_entropy[3]; 28*4882a593Smuzhiyun uint32_t hw_digctl_entropy_latched; /* 0x0a0 */ 29*4882a593Smuzhiyun uint32_t reserved_entropy_latched[3]; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun uint32_t reserved1[4]; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun mxs_reg_32(hw_digctl_microseconds) /* 0x0c0 */ 34*4882a593Smuzhiyun uint32_t hw_digctl_dbgrd; /* 0x0d0 */ 35*4882a593Smuzhiyun uint32_t reserved_hw_digctl_dbgrd[3]; 36*4882a593Smuzhiyun uint32_t hw_digctl_dbg; /* 0x0e0 */ 37*4882a593Smuzhiyun uint32_t reserved_hw_digctl_dbg[3]; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun uint32_t reserved2[4]; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun mxs_reg_32(hw_digctl_usb_loopback) /* 0x100 */ 42*4882a593Smuzhiyun mxs_reg_32(hw_digctl_ocram_status0) /* 0x110 */ 43*4882a593Smuzhiyun mxs_reg_32(hw_digctl_ocram_status1) /* 0x120 */ 44*4882a593Smuzhiyun mxs_reg_32(hw_digctl_ocram_status2) /* 0x130 */ 45*4882a593Smuzhiyun mxs_reg_32(hw_digctl_ocram_status3) /* 0x140 */ 46*4882a593Smuzhiyun mxs_reg_32(hw_digctl_ocram_status4) /* 0x150 */ 47*4882a593Smuzhiyun mxs_reg_32(hw_digctl_ocram_status5) /* 0x160 */ 48*4882a593Smuzhiyun mxs_reg_32(hw_digctl_ocram_status6) /* 0x170 */ 49*4882a593Smuzhiyun mxs_reg_32(hw_digctl_ocram_status7) /* 0x180 */ 50*4882a593Smuzhiyun mxs_reg_32(hw_digctl_ocram_status8) /* 0x190 */ 51*4882a593Smuzhiyun mxs_reg_32(hw_digctl_ocram_status9) /* 0x1a0 */ 52*4882a593Smuzhiyun mxs_reg_32(hw_digctl_ocram_status10) /* 0x1b0 */ 53*4882a593Smuzhiyun mxs_reg_32(hw_digctl_ocram_status11) /* 0x1c0 */ 54*4882a593Smuzhiyun mxs_reg_32(hw_digctl_ocram_status12) /* 0x1d0 */ 55*4882a593Smuzhiyun mxs_reg_32(hw_digctl_ocram_status13) /* 0x1e0 */ 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun uint32_t reserved3[36]; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun uint32_t hw_digctl_scratch0; /* 0x280 */ 60*4882a593Smuzhiyun uint32_t reserved_hw_digctl_scratch0[3]; 61*4882a593Smuzhiyun uint32_t hw_digctl_scratch1; /* 0x290 */ 62*4882a593Smuzhiyun uint32_t reserved_hw_digctl_scratch1[3]; 63*4882a593Smuzhiyun uint32_t hw_digctl_armcache; /* 0x2a0 */ 64*4882a593Smuzhiyun uint32_t reserved_hw_digctl_armcache[3]; 65*4882a593Smuzhiyun mxs_reg_32(hw_digctl_debug_trap) /* 0x2b0 */ 66*4882a593Smuzhiyun uint32_t hw_digctl_debug_trap_l0_addr_low; /* 0x2c0 */ 67*4882a593Smuzhiyun uint32_t reserved_hw_digctl_debug_trap_l0_addr_low[3]; 68*4882a593Smuzhiyun uint32_t hw_digctl_debug_trap_l0_addr_high; /* 0x2d0 */ 69*4882a593Smuzhiyun uint32_t reserved_hw_digctl_debug_trap_l0_addr_high[3]; 70*4882a593Smuzhiyun uint32_t hw_digctl_debug_trap_l3_addr_low; /* 0x2e0 */ 71*4882a593Smuzhiyun uint32_t reserved_hw_digctl_debug_trap_l3_addr_low[3]; 72*4882a593Smuzhiyun uint32_t hw_digctl_debug_trap_l3_addr_high; /* 0x2f0 */ 73*4882a593Smuzhiyun uint32_t reserved_hw_digctl_debug_trap_l3_addr_high[3]; 74*4882a593Smuzhiyun uint32_t hw_digctl_fsl; /* 0x300 */ 75*4882a593Smuzhiyun uint32_t reserved_hw_digctl_fsl[3]; 76*4882a593Smuzhiyun uint32_t hw_digctl_chipid; /* 0x310 */ 77*4882a593Smuzhiyun uint32_t reserved_hw_digctl_chipid[3]; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun uint32_t reserved4[4]; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun uint32_t hw_digctl_ahb_stats_select; /* 0x330 */ 82*4882a593Smuzhiyun uint32_t reserved_hw_digctl_ahb_stats_select[3]; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun uint32_t reserved5[12]; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun uint32_t hw_digctl_l1_ahb_active_cycles; /* 0x370 */ 87*4882a593Smuzhiyun uint32_t reserved_hw_digctl_l1_ahb_active_cycles[3]; 88*4882a593Smuzhiyun uint32_t hw_digctl_l1_ahb_data_stalled; /* 0x380 */ 89*4882a593Smuzhiyun uint32_t reserved_hw_digctl_l1_ahb_data_stalled[3]; 90*4882a593Smuzhiyun uint32_t hw_digctl_l1_ahb_data_cycles; /* 0x390 */ 91*4882a593Smuzhiyun uint32_t reserved_hw_digctl_l1_ahb_data_cycles[3]; 92*4882a593Smuzhiyun uint32_t hw_digctl_l2_ahb_active_cycles; /* 0x3a0 */ 93*4882a593Smuzhiyun uint32_t reserved_hw_digctl_l2_ahb_active_cycles[3]; 94*4882a593Smuzhiyun uint32_t hw_digctl_l2_ahb_data_stalled; /* 0x3b0 */ 95*4882a593Smuzhiyun uint32_t reserved_hw_digctl_l2_ahb_data_stalled[3]; 96*4882a593Smuzhiyun uint32_t hw_digctl_l2_ahb_data_cycles; /* 0x3c0 */ 97*4882a593Smuzhiyun uint32_t reserved_hw_digctl_l2_ahb_data_cycles[3]; 98*4882a593Smuzhiyun uint32_t hw_digctl_l3_ahb_active_cycles; /* 0x3d0 */ 99*4882a593Smuzhiyun uint32_t reserved_hw_digctl_l3_ahb_active_cycles[3]; 100*4882a593Smuzhiyun uint32_t hw_digctl_l3_ahb_data_stalled; /* 0x3e0 */ 101*4882a593Smuzhiyun uint32_t reserved_hw_digctl_l3_ahb_data_stalled[3]; 102*4882a593Smuzhiyun uint32_t hw_digctl_l3_ahb_data_cycles; /* 0x3f0 */ 103*4882a593Smuzhiyun uint32_t reserved_hw_digctl_l3_ahb_data_cycles[3]; 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun uint32_t reserved6[64]; 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun uint32_t hw_digctl_mpte0_loc; /* 0x500 */ 108*4882a593Smuzhiyun uint32_t reserved_hw_digctl_mpte0_loc[3]; 109*4882a593Smuzhiyun uint32_t hw_digctl_mpte1_loc; /* 0x510 */ 110*4882a593Smuzhiyun uint32_t reserved_hw_digctl_mpte1_loc[3]; 111*4882a593Smuzhiyun uint32_t hw_digctl_mpte2_loc; /* 0x520 */ 112*4882a593Smuzhiyun uint32_t reserved_hw_digctl_mpte2_loc[3]; 113*4882a593Smuzhiyun uint32_t hw_digctl_mpte3_loc; /* 0x530 */ 114*4882a593Smuzhiyun uint32_t reserved_hw_digctl_mpte3_loc[3]; 115*4882a593Smuzhiyun uint32_t hw_digctl_mpte4_loc; /* 0x540 */ 116*4882a593Smuzhiyun uint32_t reserved_hw_digctl_mpte4_loc[3]; 117*4882a593Smuzhiyun uint32_t hw_digctl_mpte5_loc; /* 0x550 */ 118*4882a593Smuzhiyun uint32_t reserved_hw_digctl_mpte5_loc[3]; 119*4882a593Smuzhiyun uint32_t hw_digctl_mpte6_loc; /* 0x560 */ 120*4882a593Smuzhiyun uint32_t reserved_hw_digctl_mpte6_loc[3]; 121*4882a593Smuzhiyun uint32_t hw_digctl_mpte7_loc; /* 0x570 */ 122*4882a593Smuzhiyun uint32_t reserved_hw_digctl_mpte7_loc[3]; 123*4882a593Smuzhiyun uint32_t hw_digctl_mpte8_loc; /* 0x580 */ 124*4882a593Smuzhiyun uint32_t reserved_hw_digctl_mpte8_loc[3]; 125*4882a593Smuzhiyun uint32_t hw_digctl_mpte9_loc; /* 0x590 */ 126*4882a593Smuzhiyun uint32_t reserved_hw_digctl_mpte9_loc[3]; 127*4882a593Smuzhiyun uint32_t hw_digctl_mpte10_loc; /* 0x5a0 */ 128*4882a593Smuzhiyun uint32_t reserved_hw_digctl_mpte10_loc[3]; 129*4882a593Smuzhiyun uint32_t hw_digctl_mpte11_loc; /* 0x5b0 */ 130*4882a593Smuzhiyun uint32_t reserved_hw_digctl_mpte11_loc[3]; 131*4882a593Smuzhiyun uint32_t hw_digctl_mpte12_loc; /* 0x5c0 */ 132*4882a593Smuzhiyun uint32_t reserved_hw_digctl_mpte12_loc[3]; 133*4882a593Smuzhiyun uint32_t hw_digctl_mpte13_loc; /* 0x5d0 */ 134*4882a593Smuzhiyun uint32_t reserved_hw_digctl_mpte13_loc[3]; 135*4882a593Smuzhiyun uint32_t hw_digctl_mpte14_loc; /* 0x5e0 */ 136*4882a593Smuzhiyun uint32_t reserved_hw_digctl_mpte14_loc[3]; 137*4882a593Smuzhiyun uint32_t hw_digctl_mpte15_loc; /* 0x5f0 */ 138*4882a593Smuzhiyun uint32_t reserved_hw_digctl_mpte15_loc[3]; 139*4882a593Smuzhiyun }; 140*4882a593Smuzhiyun #endif 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun /* Product code identification */ 143*4882a593Smuzhiyun #define HW_DIGCTL_CHIPID_MASK (0xffff << 16) 144*4882a593Smuzhiyun #define HW_DIGCTL_CHIPID_MX23 (0x3780 << 16) 145*4882a593Smuzhiyun #define HW_DIGCTL_CHIPID_MX28 (0x2800 << 16) 146*4882a593Smuzhiyun 147*4882a593Smuzhiyun #endif /* __MX28_REGS_DIGCTL_H__ */ 148