1 /* 2 * (C) Copyright 2021 Rockchip Electronics Co., Ltd. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #ifndef _ASM_ARCH_IOC_RK3528_H 7 #define _ASM_ARCH_IOC_RK3528_H 8 9 #include <common.h> 10 11 struct rk3528_gpio0_ioc { 12 uint32_t gpio0a_iomux_sel_l; /* Address Offset: 0x0000 */ 13 uint32_t gpio0a_iomux_sel_h; /* Address Offset: 0x0004 */ 14 uint32_t reserved0008[62]; /* Address Offset: 0x0008 */ 15 uint32_t gpio0a_ds[3]; /* Address Offset: 0x0100 */ 16 uint32_t reserved010c[61]; /* Address Offset: 0x010C */ 17 uint32_t gpio0a_pull; /* Address Offset: 0x0200 */ 18 uint32_t reserved0204[63]; /* Address Offset: 0x0204 */ 19 uint32_t gpio0a_ie; /* Address Offset: 0x0300 */ 20 uint32_t reserved0304[63]; /* Address Offset: 0x0304 */ 21 uint32_t gpio0a_smt; /* Address Offset: 0x0400 */ 22 uint32_t reserved0404[63]; /* Address Offset: 0x0404 */ 23 uint32_t gpio0a_sus; /* Address Offset: 0x0500 */ 24 uint32_t reserved0504[63]; /* Address Offset: 0x0504 */ 25 uint32_t gpio0a_sl; /* Address Offset: 0x0600 */ 26 uint32_t reserved0604[63]; /* Address Offset: 0x0604 */ 27 uint32_t gpio0a_od; /* Address Offset: 0x0700 */ 28 uint32_t vcc5vio_ctrl; /* Address Offset: 0x0704 */ 29 }; 30 check_member(rk3528_gpio0_ioc, vcc5vio_ctrl, 0x0704); 31 32 struct rk3528_gpio1_ioc { 33 uint32_t reserved0000[8]; /* Address Offset: 0x0000 */ 34 uint32_t gpio1a_iomux_sel_l; /* Address Offset: 0x0020 */ 35 uint32_t gpio1a_iomux_sel_h; /* Address Offset: 0x0024 */ 36 uint32_t gpio1b_iomux_sel_l; /* Address Offset: 0x0028 */ 37 uint32_t gpio1b_iomux_sel_h; /* Address Offset: 0x002C */ 38 uint32_t gpio1c_iomux_sel_l; /* Address Offset: 0x0030 */ 39 uint32_t gpio1c_iomux_sel_h; /* Address Offset: 0x0034 */ 40 uint32_t gpio1d_iomux_sel_l; /* Address Offset: 0x0038 */ 41 uint32_t gpio1d_iomux_sel_h; /* Address Offset: 0x003C */ 42 uint32_t reserved0040[56]; /* Address Offset: 0x0040 */ 43 uint32_t gpio1a_ds[4]; /* Address Offset: 0x0120 */ 44 uint32_t gpio1b_ds[4]; /* Address Offset: 0x0130 */ 45 uint32_t gpio1c_ds[4]; /* Address Offset: 0x0140 */ 46 uint32_t gpio1d_ds[4]; /* Address Offset: 0x0150 */ 47 uint32_t reserved0160[44]; /* Address Offset: 0x0160 */ 48 uint32_t gpio1a_pull; /* Address Offset: 0x0210 */ 49 uint32_t gpio1b_pull; /* Address Offset: 0x0214 */ 50 uint32_t gpio1c_pull; /* Address Offset: 0x0218 */ 51 uint32_t gpio1d_pull; /* Address Offset: 0x021C */ 52 uint32_t reserved0220[60]; /* Address Offset: 0x0220 */ 53 uint32_t gpio1a_ie; /* Address Offset: 0x0310 */ 54 uint32_t gpio1b_ie; /* Address Offset: 0x0314 */ 55 uint32_t gpio1c_ie; /* Address Offset: 0x0318 */ 56 uint32_t gpio1d_ie; /* Address Offset: 0x031C */ 57 uint32_t reserved0320[60]; /* Address Offset: 0x0320 */ 58 uint32_t gpio1a_smt; /* Address Offset: 0x0410 */ 59 uint32_t gpio1b_smt; /* Address Offset: 0x0414 */ 60 uint32_t gpio1c_smt; /* Address Offset: 0x0418 */ 61 uint32_t gpio1d_smt; /* Address Offset: 0x041C */ 62 uint32_t reserved0420[60]; /* Address Offset: 0x0420 */ 63 uint32_t gpio1a_sus; /* Address Offset: 0x0510 */ 64 uint32_t gpio1b_sus; /* Address Offset: 0x0514 */ 65 uint32_t gpio1c_sus; /* Address Offset: 0x0518 */ 66 uint32_t gpio1d_sus; /* Address Offset: 0x051C */ 67 uint32_t reserved0520[60]; /* Address Offset: 0x0520 */ 68 uint32_t gpio1a_sl; /* Address Offset: 0x0610 */ 69 uint32_t gpio1b_sl; /* Address Offset: 0x0614 */ 70 uint32_t gpio1c_sl; /* Address Offset: 0x0618 */ 71 uint32_t gpio1d_sl; /* Address Offset: 0x061C */ 72 uint32_t reserved0620[60]; /* Address Offset: 0x0620 */ 73 uint32_t gpio1a_od; /* Address Offset: 0x0710 */ 74 uint32_t gpio1b_od; /* Address Offset: 0x0714 */ 75 uint32_t gpio1c_od; /* Address Offset: 0x0718 */ 76 uint32_t gpio1d_od; /* Address Offset: 0x071C */ 77 uint32_t reserved0720[60]; /* Address Offset: 0x0720 */ 78 uint32_t vccio0_poc; /* Address Offset: 0x0810 */ 79 uint32_t reserved0814[3]; /* Address Offset: 0x0814 */ 80 uint32_t vccio1_poc; /* Address Offset: 0x0820 */ 81 }; 82 check_member(rk3528_gpio1_ioc, vccio1_poc, 0x0820); 83 84 struct rk3528_gpio2_ioc { 85 uint32_t reserved0000[16]; /* Address Offset: 0x0000 */ 86 uint32_t gpio2a_iomux_sel_l; /* Address Offset: 0x0040 */ 87 uint32_t gpio2a_iomux_sel_h; /* Address Offset: 0x0044 */ 88 uint32_t reserved0048[70]; /* Address Offset: 0x0048 */ 89 uint32_t gpio2a_ds[4]; /* Address Offset: 0x0160 */ 90 uint32_t reserved0170[44]; /* Address Offset: 0x0170 */ 91 uint32_t gpio2a_pull; /* Address Offset: 0x0220 */ 92 uint32_t reserved0224[63]; /* Address Offset: 0x0224 */ 93 uint32_t gpio2a_ie; /* Address Offset: 0x0320 */ 94 uint32_t reserved0324[63]; /* Address Offset: 0x0324 */ 95 uint32_t gpio2a_smt; /* Address Offset: 0x0420 */ 96 uint32_t reserved0424[63]; /* Address Offset: 0x0424 */ 97 uint32_t gpio2a_sus; /* Address Offset: 0x0520 */ 98 uint32_t reserved0524[63]; /* Address Offset: 0x0524 */ 99 uint32_t gpio2a_sl; /* Address Offset: 0x0620 */ 100 uint32_t reserved0624[63]; /* Address Offset: 0x0624 */ 101 uint32_t gpio2a_od; /* Address Offset: 0x0720 */ 102 uint32_t reserved0724[67]; /* Address Offset: 0x0724 */ 103 uint32_t vccio2_poc; /* Address Offset: 0x0830 */ 104 }; 105 check_member(rk3528_gpio2_ioc, vccio2_poc, 0x0830); 106 107 struct rk3528_gpio3_ioc { 108 uint32_t reserved0000[24]; /* Address Offset: 0x0000 */ 109 uint32_t gpio3a_iomux_sel_l; /* Address Offset: 0x0060 */ 110 uint32_t gpio3a_iomux_sel_h; /* Address Offset: 0x0064 */ 111 uint32_t gpio3b_iomux_sel_l; /* Address Offset: 0x0068 */ 112 uint32_t gpio3b_iomux_sel_h; /* Address Offset: 0x006C */ 113 uint32_t gpio3c_iomux_sel_l; /* Address Offset: 0x0070 */ 114 uint32_t reserved0074[71]; /* Address Offset: 0x0074 */ 115 uint32_t gpio3a_ds[4]; /* Address Offset: 0x0190 */ 116 uint32_t gpio3b_ds[4]; /* Address Offset: 0x01A0 */ 117 uint32_t gpio3c_ds[2]; /* Address Offset: 0x01B0 */ 118 uint32_t reserved01b8[30]; /* Address Offset: 0x01B8 */ 119 uint32_t gpio3a_pull; /* Address Offset: 0x0230 */ 120 uint32_t gpio3b_pull; /* Address Offset: 0x0234 */ 121 uint32_t gpio3c_pull; /* Address Offset: 0x0238 */ 122 uint32_t reserved023c[61]; /* Address Offset: 0x023C */ 123 uint32_t gpio3a_ie; /* Address Offset: 0x0330 */ 124 uint32_t gpio3b_ie; /* Address Offset: 0x0334 */ 125 uint32_t gpio3c_ie; /* Address Offset: 0x0338 */ 126 uint32_t reserved033c[61]; /* Address Offset: 0x033C */ 127 uint32_t gpio3a_smt; /* Address Offset: 0x0430 */ 128 uint32_t gpio3b_smt; /* Address Offset: 0x0434 */ 129 uint32_t gpio3c_smt; /* Address Offset: 0x0438 */ 130 uint32_t reserved043c[61]; /* Address Offset: 0x043C */ 131 uint32_t gpio3a_sus; /* Address Offset: 0x0530 */ 132 uint32_t gpio3b_sus; /* Address Offset: 0x0534 */ 133 uint32_t gpio3c_sus; /* Address Offset: 0x0538 */ 134 uint32_t reserved053c[61]; /* Address Offset: 0x053C */ 135 uint32_t gpio3a_sl; /* Address Offset: 0x0630 */ 136 uint32_t gpio3b_sl; /* Address Offset: 0x0634 */ 137 uint32_t gpio3c_sl; /* Address Offset: 0x0638 */ 138 uint32_t reserved063c[61]; /* Address Offset: 0x063C */ 139 uint32_t gpio3a_od; /* Address Offset: 0x0730 */ 140 uint32_t gpio3b_od; /* Address Offset: 0x0734 */ 141 uint32_t gpio3c_od; /* Address Offset: 0x0738 */ 142 uint32_t reserved073c[65]; /* Address Offset: 0x073C */ 143 uint32_t vccio3_poc; /* Address Offset: 0x0840 */ 144 }; 145 check_member(rk3528_gpio3_ioc, vccio3_poc, 0x0840); 146 147 struct rk3528_gpio4_ioc { 148 uint32_t reserved0000[32]; /* Address Offset: 0x0000 */ 149 uint32_t gpio4a_iomux_sel_l; /* Address Offset: 0x0080 */ 150 uint32_t gpio4a_iomux_sel_h; /* Address Offset: 0x0084 */ 151 uint32_t gpio4b_iomux_sel_l; /* Address Offset: 0x0088 */ 152 uint32_t gpio4b_iomux_sel_h; /* Address Offset: 0x008C */ 153 uint32_t gpio4c_iomux_sel_l; /* Address Offset: 0x0090 */ 154 uint32_t gpio4c_iomux_sel_h; /* Address Offset: 0x0094 */ 155 uint32_t gpio4d_iomux_sel_l; /* Address Offset: 0x0098 */ 156 uint32_t reserved009c[73]; /* Address Offset: 0x009C */ 157 uint32_t gpio4a_ds[4]; /* Address Offset: 0x01C0 */ 158 uint32_t gpio4b_ds[4]; /* Address Offset: 0x01D0 */ 159 uint32_t gpio4c_ds[4]; /* Address Offset: 0x01E0 */ 160 uint32_t gpio4d_ds[1]; /* Address Offset: 0x01F0 */ 161 uint32_t reserved01f4[19]; /* Address Offset: 0x01F4 */ 162 uint32_t gpio4a_pull; /* Address Offset: 0x0240 */ 163 uint32_t gpio4b_pull; /* Address Offset: 0x0244 */ 164 uint32_t gpio4c_pull; /* Address Offset: 0x0248 */ 165 uint32_t gpio4d_pull; /* Address Offset: 0x024C */ 166 uint32_t reserved0250[60]; /* Address Offset: 0x0250 */ 167 uint32_t gpio4a_ie; /* Address Offset: 0x0340 */ 168 uint32_t gpio4b_ie; /* Address Offset: 0x0344 */ 169 uint32_t gpio4c_ie; /* Address Offset: 0x0348 */ 170 uint32_t gpio4d_ie; /* Address Offset: 0x034C */ 171 uint32_t reserved0350[60]; /* Address Offset: 0x0350 */ 172 uint32_t gpio4a_smt; /* Address Offset: 0x0440 */ 173 uint32_t gpio4b_smt; /* Address Offset: 0x0444 */ 174 uint32_t gpio4c_smt; /* Address Offset: 0x0448 */ 175 uint32_t gpio4d_smt; /* Address Offset: 0x044C */ 176 uint32_t reserved0450[60]; /* Address Offset: 0x0450 */ 177 uint32_t gpio4a_sus; /* Address Offset: 0x0540 */ 178 uint32_t gpio4b_sus; /* Address Offset: 0x0544 */ 179 uint32_t gpio4c_sus; /* Address Offset: 0x0548 */ 180 uint32_t gpio4d_sus; /* Address Offset: 0x054C */ 181 uint32_t reserved0550[60]; /* Address Offset: 0x0550 */ 182 uint32_t gpio4a_sl; /* Address Offset: 0x0640 */ 183 uint32_t gpio4b_sl; /* Address Offset: 0x0644 */ 184 uint32_t gpio4c_sl; /* Address Offset: 0x0648 */ 185 uint32_t gpio4d_sl; /* Address Offset: 0x064C */ 186 uint32_t reserved0650[60]; /* Address Offset: 0x0650 */ 187 uint32_t gpio4a_od; /* Address Offset: 0x0740 */ 188 uint32_t gpio4b_od; /* Address Offset: 0x0744 */ 189 uint32_t gpio4c_od; /* Address Offset: 0x0748 */ 190 uint32_t gpio4d_od; /* Address Offset: 0x074C */ 191 uint32_t reserved0750[64]; /* Address Offset: 0x0750 */ 192 uint32_t vccio4_poc; /* Address Offset: 0x0850 */ 193 }; 194 check_member(rk3528_gpio4_ioc, vccio4_poc, 0x0850); 195 #endif 196 197