1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2021 Rockchip Electronics Co., Ltd. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun #ifndef _ASM_ARCH_IOC_RK3588_H 7*4882a593Smuzhiyun #define _ASM_ARCH_IOC_RK3588_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <common.h> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun struct rk3588_bus_ioc { 12*4882a593Smuzhiyun uint32_t reserved0000[3]; /* Address Offset: 0x0000 */ 13*4882a593Smuzhiyun uint32_t gpio0b_iomux_sel_h; /* Address Offset: 0x000C */ 14*4882a593Smuzhiyun uint32_t gpio0c_iomux_sel_l; /* Address Offset: 0x0010 */ 15*4882a593Smuzhiyun uint32_t gpio0c_iomux_sel_h; /* Address Offset: 0x0014 */ 16*4882a593Smuzhiyun uint32_t gpio0d_iomux_sel_l; /* Address Offset: 0x0018 */ 17*4882a593Smuzhiyun uint32_t gpio0d_iomux_sel_h; /* Address Offset: 0x001C */ 18*4882a593Smuzhiyun uint32_t gpio1a_iomux_sel_l; /* Address Offset: 0x0020 */ 19*4882a593Smuzhiyun uint32_t gpio1a_iomux_sel_h; /* Address Offset: 0x0024 */ 20*4882a593Smuzhiyun uint32_t gpio1b_iomux_sel_l; /* Address Offset: 0x0028 */ 21*4882a593Smuzhiyun uint32_t gpio1b_iomux_sel_h; /* Address Offset: 0x002C */ 22*4882a593Smuzhiyun uint32_t gpio1c_iomux_sel_l; /* Address Offset: 0x0030 */ 23*4882a593Smuzhiyun uint32_t gpio1c_iomux_sel_h; /* Address Offset: 0x0034 */ 24*4882a593Smuzhiyun uint32_t gpio1d_iomux_sel_l; /* Address Offset: 0x0038 */ 25*4882a593Smuzhiyun uint32_t gpio1d_iomux_sel_h; /* Address Offset: 0x003C */ 26*4882a593Smuzhiyun uint32_t gpio2a_iomux_sel_l; /* Address Offset: 0x0040 */ 27*4882a593Smuzhiyun uint32_t gpio2a_iomux_sel_h; /* Address Offset: 0x0044 */ 28*4882a593Smuzhiyun uint32_t gpio2b_iomux_sel_l; /* Address Offset: 0x0048 */ 29*4882a593Smuzhiyun uint32_t gpio2b_iomux_sel_h; /* Address Offset: 0x004C */ 30*4882a593Smuzhiyun uint32_t gpio2c_iomux_sel_l; /* Address Offset: 0x0050 */ 31*4882a593Smuzhiyun uint32_t gpio2c_iomux_sel_h; /* Address Offset: 0x0054 */ 32*4882a593Smuzhiyun uint32_t gpio2d_iomux_sel_l; /* Address Offset: 0x0058 */ 33*4882a593Smuzhiyun uint32_t gpio2d_iomux_sel_h; /* Address Offset: 0x005C */ 34*4882a593Smuzhiyun uint32_t gpio3a_iomux_sel_l; /* Address Offset: 0x0060 */ 35*4882a593Smuzhiyun uint32_t gpio3a_iomux_sel_h; /* Address Offset: 0x0064 */ 36*4882a593Smuzhiyun uint32_t gpio3b_iomux_sel_l; /* Address Offset: 0x0068 */ 37*4882a593Smuzhiyun uint32_t gpio3b_iomux_sel_h; /* Address Offset: 0x006C */ 38*4882a593Smuzhiyun uint32_t gpio3c_iomux_sel_l; /* Address Offset: 0x0070 */ 39*4882a593Smuzhiyun uint32_t gpio3c_iomux_sel_h; /* Address Offset: 0x0074 */ 40*4882a593Smuzhiyun uint32_t gpio3d_iomux_sel_l; /* Address Offset: 0x0078 */ 41*4882a593Smuzhiyun uint32_t gpio3d_iomux_sel_h; /* Address Offset: 0x007C */ 42*4882a593Smuzhiyun uint32_t gpio4a_iomux_sel_l; /* Address Offset: 0x0080 */ 43*4882a593Smuzhiyun uint32_t gpio4a_iomux_sel_h; /* Address Offset: 0x0084 */ 44*4882a593Smuzhiyun uint32_t gpio4b_iomux_sel_l; /* Address Offset: 0x0088 */ 45*4882a593Smuzhiyun uint32_t gpio4b_iomux_sel_h; /* Address Offset: 0x008C */ 46*4882a593Smuzhiyun uint32_t gpio4c_iomux_sel_l; /* Address Offset: 0x0090 */ 47*4882a593Smuzhiyun uint32_t gpio4c_iomux_sel_h; /* Address Offset: 0x0094 */ 48*4882a593Smuzhiyun uint32_t gpio4d_iomux_sel_l; /* Address Offset: 0x0098 */ 49*4882a593Smuzhiyun uint32_t gpio4d_iomux_sel_h; /* Address Offset: 0x009C */ 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun check_member(rk3588_bus_ioc, gpio4d_iomux_sel_h, 0x009C); 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun struct rk3588_pmu1_ioc { 55*4882a593Smuzhiyun uint32_t gpio0a_iomux_sel_l; /* Address Offset: 0x0000 */ 56*4882a593Smuzhiyun uint32_t gpio0a_iomux_sel_h; /* Address Offset: 0x0004 */ 57*4882a593Smuzhiyun uint32_t gpio0b_iomux_sel_l; /* Address Offset: 0x0008 */ 58*4882a593Smuzhiyun uint32_t reserved0012; /* Address Offset: 0x000C */ 59*4882a593Smuzhiyun uint32_t gpio0a_ds_l; /* Address Offset: 0x0010 */ 60*4882a593Smuzhiyun uint32_t gpio0a_ds_h; /* Address Offset: 0x0014 */ 61*4882a593Smuzhiyun uint32_t gpio0b_ds_l; /* Address Offset: 0x0018 */ 62*4882a593Smuzhiyun uint32_t reserved0028; /* Address Offset: 0x001C */ 63*4882a593Smuzhiyun uint32_t gpio0a_p; /* Address Offset: 0x0020 */ 64*4882a593Smuzhiyun uint32_t gpio0b_p; /* Address Offset: 0x0024 */ 65*4882a593Smuzhiyun uint32_t gpio0a_ie; /* Address Offset: 0x0028 */ 66*4882a593Smuzhiyun uint32_t gpio0b_ie; /* Address Offset: 0x002C */ 67*4882a593Smuzhiyun uint32_t gpio0a_smt; /* Address Offset: 0x0030 */ 68*4882a593Smuzhiyun uint32_t gpio0b_smt; /* Address Offset: 0x0034 */ 69*4882a593Smuzhiyun uint32_t gpio0a_pdis; /* Address Offset: 0x0038 */ 70*4882a593Smuzhiyun uint32_t gpio0b_pdis; /* Address Offset: 0x003C */ 71*4882a593Smuzhiyun uint32_t xin_con; /* Address Offset: 0x0040 */ 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun check_member(rk3588_pmu1_ioc, xin_con, 0x0040); 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun struct rk3588_pmu2_ioc { 76*4882a593Smuzhiyun uint32_t gpio0b_iomux_sel_h; /* Address Offset: 0x0000 */ 77*4882a593Smuzhiyun uint32_t gpio0c_iomux_sel_l; /* Address Offset: 0x0004 */ 78*4882a593Smuzhiyun uint32_t gpio0c_iomux_sel_h; /* Address Offset: 0x0008 */ 79*4882a593Smuzhiyun uint32_t gpio0d_iomux_sel_l; /* Address Offset: 0x000C */ 80*4882a593Smuzhiyun uint32_t gpio0d_iomux_sel_h; /* Address Offset: 0x0010 */ 81*4882a593Smuzhiyun uint32_t gpio0b_ds_h; /* Address Offset: 0x0014 */ 82*4882a593Smuzhiyun uint32_t gpio0c_ds_l; /* Address Offset: 0x0018 */ 83*4882a593Smuzhiyun uint32_t gpio0c_ds_h; /* Address Offset: 0x001C */ 84*4882a593Smuzhiyun uint32_t gpio0d_ds_l; /* Address Offset: 0x0020 */ 85*4882a593Smuzhiyun uint32_t gpio0d_ds_h; /* Address Offset: 0x0024 */ 86*4882a593Smuzhiyun uint32_t gpio0b_p; /* Address Offset: 0x0028 */ 87*4882a593Smuzhiyun uint32_t gpio0c_p; /* Address Offset: 0x002C */ 88*4882a593Smuzhiyun uint32_t gpio0d_p; /* Address Offset: 0x0030 */ 89*4882a593Smuzhiyun uint32_t gpio0b_ie; /* Address Offset: 0x0034 */ 90*4882a593Smuzhiyun uint32_t gpio0c_ie; /* Address Offset: 0x0038 */ 91*4882a593Smuzhiyun uint32_t gpio0d_ie; /* Address Offset: 0x003C */ 92*4882a593Smuzhiyun uint32_t gpio0b_smt; /* Address Offset: 0x0040 */ 93*4882a593Smuzhiyun uint32_t gpio0c_smt; /* Address Offset: 0x0044 */ 94*4882a593Smuzhiyun uint32_t gpio0d_smt; /* Address Offset: 0x0048 */ 95*4882a593Smuzhiyun uint32_t gpio0b_pdis; /* Address Offset: 0x004C */ 96*4882a593Smuzhiyun uint32_t gpio0c_pdis; /* Address Offset: 0x0050 */ 97*4882a593Smuzhiyun uint32_t gpio0d_pdis; /* Address Offset: 0x0054 */ 98*4882a593Smuzhiyun }; 99*4882a593Smuzhiyun check_member(rk3588_pmu2_ioc, gpio0d_pdis, 0x0054); 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun #endif 102*4882a593Smuzhiyun 103