1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2021 Rockchip Electronics Co., Ltd. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun #ifndef _ASM_ARCH_IOC_RK3528_H 7*4882a593Smuzhiyun #define _ASM_ARCH_IOC_RK3528_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <common.h> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun struct rk3528_gpio0_ioc { 12*4882a593Smuzhiyun uint32_t gpio0a_iomux_sel_l; /* Address Offset: 0x0000 */ 13*4882a593Smuzhiyun uint32_t gpio0a_iomux_sel_h; /* Address Offset: 0x0004 */ 14*4882a593Smuzhiyun uint32_t reserved0008[62]; /* Address Offset: 0x0008 */ 15*4882a593Smuzhiyun uint32_t gpio0a_ds[3]; /* Address Offset: 0x0100 */ 16*4882a593Smuzhiyun uint32_t reserved010c[61]; /* Address Offset: 0x010C */ 17*4882a593Smuzhiyun uint32_t gpio0a_pull; /* Address Offset: 0x0200 */ 18*4882a593Smuzhiyun uint32_t reserved0204[63]; /* Address Offset: 0x0204 */ 19*4882a593Smuzhiyun uint32_t gpio0a_ie; /* Address Offset: 0x0300 */ 20*4882a593Smuzhiyun uint32_t reserved0304[63]; /* Address Offset: 0x0304 */ 21*4882a593Smuzhiyun uint32_t gpio0a_smt; /* Address Offset: 0x0400 */ 22*4882a593Smuzhiyun uint32_t reserved0404[63]; /* Address Offset: 0x0404 */ 23*4882a593Smuzhiyun uint32_t gpio0a_sus; /* Address Offset: 0x0500 */ 24*4882a593Smuzhiyun uint32_t reserved0504[63]; /* Address Offset: 0x0504 */ 25*4882a593Smuzhiyun uint32_t gpio0a_sl; /* Address Offset: 0x0600 */ 26*4882a593Smuzhiyun uint32_t reserved0604[63]; /* Address Offset: 0x0604 */ 27*4882a593Smuzhiyun uint32_t gpio0a_od; /* Address Offset: 0x0700 */ 28*4882a593Smuzhiyun uint32_t vcc5vio_ctrl; /* Address Offset: 0x0704 */ 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun check_member(rk3528_gpio0_ioc, vcc5vio_ctrl, 0x0704); 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun struct rk3528_gpio1_ioc { 33*4882a593Smuzhiyun uint32_t reserved0000[8]; /* Address Offset: 0x0000 */ 34*4882a593Smuzhiyun uint32_t gpio1a_iomux_sel_l; /* Address Offset: 0x0020 */ 35*4882a593Smuzhiyun uint32_t gpio1a_iomux_sel_h; /* Address Offset: 0x0024 */ 36*4882a593Smuzhiyun uint32_t gpio1b_iomux_sel_l; /* Address Offset: 0x0028 */ 37*4882a593Smuzhiyun uint32_t gpio1b_iomux_sel_h; /* Address Offset: 0x002C */ 38*4882a593Smuzhiyun uint32_t gpio1c_iomux_sel_l; /* Address Offset: 0x0030 */ 39*4882a593Smuzhiyun uint32_t gpio1c_iomux_sel_h; /* Address Offset: 0x0034 */ 40*4882a593Smuzhiyun uint32_t gpio1d_iomux_sel_l; /* Address Offset: 0x0038 */ 41*4882a593Smuzhiyun uint32_t gpio1d_iomux_sel_h; /* Address Offset: 0x003C */ 42*4882a593Smuzhiyun uint32_t reserved0040[56]; /* Address Offset: 0x0040 */ 43*4882a593Smuzhiyun uint32_t gpio1a_ds[4]; /* Address Offset: 0x0120 */ 44*4882a593Smuzhiyun uint32_t gpio1b_ds[4]; /* Address Offset: 0x0130 */ 45*4882a593Smuzhiyun uint32_t gpio1c_ds[4]; /* Address Offset: 0x0140 */ 46*4882a593Smuzhiyun uint32_t gpio1d_ds[4]; /* Address Offset: 0x0150 */ 47*4882a593Smuzhiyun uint32_t reserved0160[44]; /* Address Offset: 0x0160 */ 48*4882a593Smuzhiyun uint32_t gpio1a_pull; /* Address Offset: 0x0210 */ 49*4882a593Smuzhiyun uint32_t gpio1b_pull; /* Address Offset: 0x0214 */ 50*4882a593Smuzhiyun uint32_t gpio1c_pull; /* Address Offset: 0x0218 */ 51*4882a593Smuzhiyun uint32_t gpio1d_pull; /* Address Offset: 0x021C */ 52*4882a593Smuzhiyun uint32_t reserved0220[60]; /* Address Offset: 0x0220 */ 53*4882a593Smuzhiyun uint32_t gpio1a_ie; /* Address Offset: 0x0310 */ 54*4882a593Smuzhiyun uint32_t gpio1b_ie; /* Address Offset: 0x0314 */ 55*4882a593Smuzhiyun uint32_t gpio1c_ie; /* Address Offset: 0x0318 */ 56*4882a593Smuzhiyun uint32_t gpio1d_ie; /* Address Offset: 0x031C */ 57*4882a593Smuzhiyun uint32_t reserved0320[60]; /* Address Offset: 0x0320 */ 58*4882a593Smuzhiyun uint32_t gpio1a_smt; /* Address Offset: 0x0410 */ 59*4882a593Smuzhiyun uint32_t gpio1b_smt; /* Address Offset: 0x0414 */ 60*4882a593Smuzhiyun uint32_t gpio1c_smt; /* Address Offset: 0x0418 */ 61*4882a593Smuzhiyun uint32_t gpio1d_smt; /* Address Offset: 0x041C */ 62*4882a593Smuzhiyun uint32_t reserved0420[60]; /* Address Offset: 0x0420 */ 63*4882a593Smuzhiyun uint32_t gpio1a_sus; /* Address Offset: 0x0510 */ 64*4882a593Smuzhiyun uint32_t gpio1b_sus; /* Address Offset: 0x0514 */ 65*4882a593Smuzhiyun uint32_t gpio1c_sus; /* Address Offset: 0x0518 */ 66*4882a593Smuzhiyun uint32_t gpio1d_sus; /* Address Offset: 0x051C */ 67*4882a593Smuzhiyun uint32_t reserved0520[60]; /* Address Offset: 0x0520 */ 68*4882a593Smuzhiyun uint32_t gpio1a_sl; /* Address Offset: 0x0610 */ 69*4882a593Smuzhiyun uint32_t gpio1b_sl; /* Address Offset: 0x0614 */ 70*4882a593Smuzhiyun uint32_t gpio1c_sl; /* Address Offset: 0x0618 */ 71*4882a593Smuzhiyun uint32_t gpio1d_sl; /* Address Offset: 0x061C */ 72*4882a593Smuzhiyun uint32_t reserved0620[60]; /* Address Offset: 0x0620 */ 73*4882a593Smuzhiyun uint32_t gpio1a_od; /* Address Offset: 0x0710 */ 74*4882a593Smuzhiyun uint32_t gpio1b_od; /* Address Offset: 0x0714 */ 75*4882a593Smuzhiyun uint32_t gpio1c_od; /* Address Offset: 0x0718 */ 76*4882a593Smuzhiyun uint32_t gpio1d_od; /* Address Offset: 0x071C */ 77*4882a593Smuzhiyun uint32_t reserved0720[60]; /* Address Offset: 0x0720 */ 78*4882a593Smuzhiyun uint32_t vccio0_poc; /* Address Offset: 0x0810 */ 79*4882a593Smuzhiyun uint32_t reserved0814[3]; /* Address Offset: 0x0814 */ 80*4882a593Smuzhiyun uint32_t vccio1_poc; /* Address Offset: 0x0820 */ 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun check_member(rk3528_gpio1_ioc, vccio1_poc, 0x0820); 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun struct rk3528_gpio2_ioc { 85*4882a593Smuzhiyun uint32_t reserved0000[16]; /* Address Offset: 0x0000 */ 86*4882a593Smuzhiyun uint32_t gpio2a_iomux_sel_l; /* Address Offset: 0x0040 */ 87*4882a593Smuzhiyun uint32_t gpio2a_iomux_sel_h; /* Address Offset: 0x0044 */ 88*4882a593Smuzhiyun uint32_t reserved0048[70]; /* Address Offset: 0x0048 */ 89*4882a593Smuzhiyun uint32_t gpio2a_ds[4]; /* Address Offset: 0x0160 */ 90*4882a593Smuzhiyun uint32_t reserved0170[44]; /* Address Offset: 0x0170 */ 91*4882a593Smuzhiyun uint32_t gpio2a_pull; /* Address Offset: 0x0220 */ 92*4882a593Smuzhiyun uint32_t reserved0224[63]; /* Address Offset: 0x0224 */ 93*4882a593Smuzhiyun uint32_t gpio2a_ie; /* Address Offset: 0x0320 */ 94*4882a593Smuzhiyun uint32_t reserved0324[63]; /* Address Offset: 0x0324 */ 95*4882a593Smuzhiyun uint32_t gpio2a_smt; /* Address Offset: 0x0420 */ 96*4882a593Smuzhiyun uint32_t reserved0424[63]; /* Address Offset: 0x0424 */ 97*4882a593Smuzhiyun uint32_t gpio2a_sus; /* Address Offset: 0x0520 */ 98*4882a593Smuzhiyun uint32_t reserved0524[63]; /* Address Offset: 0x0524 */ 99*4882a593Smuzhiyun uint32_t gpio2a_sl; /* Address Offset: 0x0620 */ 100*4882a593Smuzhiyun uint32_t reserved0624[63]; /* Address Offset: 0x0624 */ 101*4882a593Smuzhiyun uint32_t gpio2a_od; /* Address Offset: 0x0720 */ 102*4882a593Smuzhiyun uint32_t reserved0724[67]; /* Address Offset: 0x0724 */ 103*4882a593Smuzhiyun uint32_t vccio2_poc; /* Address Offset: 0x0830 */ 104*4882a593Smuzhiyun }; 105*4882a593Smuzhiyun check_member(rk3528_gpio2_ioc, vccio2_poc, 0x0830); 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun struct rk3528_gpio3_ioc { 108*4882a593Smuzhiyun uint32_t reserved0000[24]; /* Address Offset: 0x0000 */ 109*4882a593Smuzhiyun uint32_t gpio3a_iomux_sel_l; /* Address Offset: 0x0060 */ 110*4882a593Smuzhiyun uint32_t gpio3a_iomux_sel_h; /* Address Offset: 0x0064 */ 111*4882a593Smuzhiyun uint32_t gpio3b_iomux_sel_l; /* Address Offset: 0x0068 */ 112*4882a593Smuzhiyun uint32_t gpio3b_iomux_sel_h; /* Address Offset: 0x006C */ 113*4882a593Smuzhiyun uint32_t gpio3c_iomux_sel_l; /* Address Offset: 0x0070 */ 114*4882a593Smuzhiyun uint32_t reserved0074[71]; /* Address Offset: 0x0074 */ 115*4882a593Smuzhiyun uint32_t gpio3a_ds[4]; /* Address Offset: 0x0190 */ 116*4882a593Smuzhiyun uint32_t gpio3b_ds[4]; /* Address Offset: 0x01A0 */ 117*4882a593Smuzhiyun uint32_t gpio3c_ds[2]; /* Address Offset: 0x01B0 */ 118*4882a593Smuzhiyun uint32_t reserved01b8[30]; /* Address Offset: 0x01B8 */ 119*4882a593Smuzhiyun uint32_t gpio3a_pull; /* Address Offset: 0x0230 */ 120*4882a593Smuzhiyun uint32_t gpio3b_pull; /* Address Offset: 0x0234 */ 121*4882a593Smuzhiyun uint32_t gpio3c_pull; /* Address Offset: 0x0238 */ 122*4882a593Smuzhiyun uint32_t reserved023c[61]; /* Address Offset: 0x023C */ 123*4882a593Smuzhiyun uint32_t gpio3a_ie; /* Address Offset: 0x0330 */ 124*4882a593Smuzhiyun uint32_t gpio3b_ie; /* Address Offset: 0x0334 */ 125*4882a593Smuzhiyun uint32_t gpio3c_ie; /* Address Offset: 0x0338 */ 126*4882a593Smuzhiyun uint32_t reserved033c[61]; /* Address Offset: 0x033C */ 127*4882a593Smuzhiyun uint32_t gpio3a_smt; /* Address Offset: 0x0430 */ 128*4882a593Smuzhiyun uint32_t gpio3b_smt; /* Address Offset: 0x0434 */ 129*4882a593Smuzhiyun uint32_t gpio3c_smt; /* Address Offset: 0x0438 */ 130*4882a593Smuzhiyun uint32_t reserved043c[61]; /* Address Offset: 0x043C */ 131*4882a593Smuzhiyun uint32_t gpio3a_sus; /* Address Offset: 0x0530 */ 132*4882a593Smuzhiyun uint32_t gpio3b_sus; /* Address Offset: 0x0534 */ 133*4882a593Smuzhiyun uint32_t gpio3c_sus; /* Address Offset: 0x0538 */ 134*4882a593Smuzhiyun uint32_t reserved053c[61]; /* Address Offset: 0x053C */ 135*4882a593Smuzhiyun uint32_t gpio3a_sl; /* Address Offset: 0x0630 */ 136*4882a593Smuzhiyun uint32_t gpio3b_sl; /* Address Offset: 0x0634 */ 137*4882a593Smuzhiyun uint32_t gpio3c_sl; /* Address Offset: 0x0638 */ 138*4882a593Smuzhiyun uint32_t reserved063c[61]; /* Address Offset: 0x063C */ 139*4882a593Smuzhiyun uint32_t gpio3a_od; /* Address Offset: 0x0730 */ 140*4882a593Smuzhiyun uint32_t gpio3b_od; /* Address Offset: 0x0734 */ 141*4882a593Smuzhiyun uint32_t gpio3c_od; /* Address Offset: 0x0738 */ 142*4882a593Smuzhiyun uint32_t reserved073c[65]; /* Address Offset: 0x073C */ 143*4882a593Smuzhiyun uint32_t vccio3_poc; /* Address Offset: 0x0840 */ 144*4882a593Smuzhiyun }; 145*4882a593Smuzhiyun check_member(rk3528_gpio3_ioc, vccio3_poc, 0x0840); 146*4882a593Smuzhiyun 147*4882a593Smuzhiyun struct rk3528_gpio4_ioc { 148*4882a593Smuzhiyun uint32_t reserved0000[32]; /* Address Offset: 0x0000 */ 149*4882a593Smuzhiyun uint32_t gpio4a_iomux_sel_l; /* Address Offset: 0x0080 */ 150*4882a593Smuzhiyun uint32_t gpio4a_iomux_sel_h; /* Address Offset: 0x0084 */ 151*4882a593Smuzhiyun uint32_t gpio4b_iomux_sel_l; /* Address Offset: 0x0088 */ 152*4882a593Smuzhiyun uint32_t gpio4b_iomux_sel_h; /* Address Offset: 0x008C */ 153*4882a593Smuzhiyun uint32_t gpio4c_iomux_sel_l; /* Address Offset: 0x0090 */ 154*4882a593Smuzhiyun uint32_t gpio4c_iomux_sel_h; /* Address Offset: 0x0094 */ 155*4882a593Smuzhiyun uint32_t gpio4d_iomux_sel_l; /* Address Offset: 0x0098 */ 156*4882a593Smuzhiyun uint32_t reserved009c[73]; /* Address Offset: 0x009C */ 157*4882a593Smuzhiyun uint32_t gpio4a_ds[4]; /* Address Offset: 0x01C0 */ 158*4882a593Smuzhiyun uint32_t gpio4b_ds[4]; /* Address Offset: 0x01D0 */ 159*4882a593Smuzhiyun uint32_t gpio4c_ds[4]; /* Address Offset: 0x01E0 */ 160*4882a593Smuzhiyun uint32_t gpio4d_ds[1]; /* Address Offset: 0x01F0 */ 161*4882a593Smuzhiyun uint32_t reserved01f4[19]; /* Address Offset: 0x01F4 */ 162*4882a593Smuzhiyun uint32_t gpio4a_pull; /* Address Offset: 0x0240 */ 163*4882a593Smuzhiyun uint32_t gpio4b_pull; /* Address Offset: 0x0244 */ 164*4882a593Smuzhiyun uint32_t gpio4c_pull; /* Address Offset: 0x0248 */ 165*4882a593Smuzhiyun uint32_t gpio4d_pull; /* Address Offset: 0x024C */ 166*4882a593Smuzhiyun uint32_t reserved0250[60]; /* Address Offset: 0x0250 */ 167*4882a593Smuzhiyun uint32_t gpio4a_ie; /* Address Offset: 0x0340 */ 168*4882a593Smuzhiyun uint32_t gpio4b_ie; /* Address Offset: 0x0344 */ 169*4882a593Smuzhiyun uint32_t gpio4c_ie; /* Address Offset: 0x0348 */ 170*4882a593Smuzhiyun uint32_t gpio4d_ie; /* Address Offset: 0x034C */ 171*4882a593Smuzhiyun uint32_t reserved0350[60]; /* Address Offset: 0x0350 */ 172*4882a593Smuzhiyun uint32_t gpio4a_smt; /* Address Offset: 0x0440 */ 173*4882a593Smuzhiyun uint32_t gpio4b_smt; /* Address Offset: 0x0444 */ 174*4882a593Smuzhiyun uint32_t gpio4c_smt; /* Address Offset: 0x0448 */ 175*4882a593Smuzhiyun uint32_t gpio4d_smt; /* Address Offset: 0x044C */ 176*4882a593Smuzhiyun uint32_t reserved0450[60]; /* Address Offset: 0x0450 */ 177*4882a593Smuzhiyun uint32_t gpio4a_sus; /* Address Offset: 0x0540 */ 178*4882a593Smuzhiyun uint32_t gpio4b_sus; /* Address Offset: 0x0544 */ 179*4882a593Smuzhiyun uint32_t gpio4c_sus; /* Address Offset: 0x0548 */ 180*4882a593Smuzhiyun uint32_t gpio4d_sus; /* Address Offset: 0x054C */ 181*4882a593Smuzhiyun uint32_t reserved0550[60]; /* Address Offset: 0x0550 */ 182*4882a593Smuzhiyun uint32_t gpio4a_sl; /* Address Offset: 0x0640 */ 183*4882a593Smuzhiyun uint32_t gpio4b_sl; /* Address Offset: 0x0644 */ 184*4882a593Smuzhiyun uint32_t gpio4c_sl; /* Address Offset: 0x0648 */ 185*4882a593Smuzhiyun uint32_t gpio4d_sl; /* Address Offset: 0x064C */ 186*4882a593Smuzhiyun uint32_t reserved0650[60]; /* Address Offset: 0x0650 */ 187*4882a593Smuzhiyun uint32_t gpio4a_od; /* Address Offset: 0x0740 */ 188*4882a593Smuzhiyun uint32_t gpio4b_od; /* Address Offset: 0x0744 */ 189*4882a593Smuzhiyun uint32_t gpio4c_od; /* Address Offset: 0x0748 */ 190*4882a593Smuzhiyun uint32_t gpio4d_od; /* Address Offset: 0x074C */ 191*4882a593Smuzhiyun uint32_t reserved0750[64]; /* Address Offset: 0x0750 */ 192*4882a593Smuzhiyun uint32_t vccio4_poc; /* Address Offset: 0x0850 */ 193*4882a593Smuzhiyun }; 194*4882a593Smuzhiyun check_member(rk3528_gpio4_ioc, vccio4_poc, 0x0850); 195*4882a593Smuzhiyun #endif 196*4882a593Smuzhiyun 197