1 /* 2 * (C) Copyright 2022 Rockchip Electronics Co., Ltd. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #ifndef _ASM_ARCH_IOC_RK3562_H 7 #define _ASM_ARCH_IOC_RK3562_H 8 9 #include <common.h> 10 11 struct rk3562_ioc { 12 uint32_t gpio1a_iomux_sel_l; /* Address Offset: 0x0000 */ 13 uint32_t gpio1a_iomux_sel_h; /* Address Offset: 0x0004 */ 14 uint32_t gpio1b_iomux_sel_l; /* Address Offset: 0x0008 */ 15 uint32_t gpio1b_iomux_sel_h; /* Address Offset: 0x000C */ 16 uint32_t gpio1c_iomux_sel_l; /* Address Offset: 0x0010 */ 17 uint32_t gpio1c_iomux_sel_h; /* Address Offset: 0x0014 */ 18 uint32_t gpio1d_iomux_sel_l; /* Address Offset: 0x0018 */ 19 uint32_t gpio1d_iomux_sel_h; /* Address Offset: 0x001C */ 20 uint32_t gpio2a_iomux_sel_l; /* Address Offset: 0x0020 */ 21 uint32_t reserved0024[23]; /* Address Offset: 0x0024 */ 22 uint32_t gpio1a_p; /* Address Offset: 0x0080 */ 23 uint32_t gpio1b_p; /* Address Offset: 0x0084 */ 24 uint32_t gpio1c_p; /* Address Offset: 0x0088 */ 25 uint32_t gpio1d_p; /* Address Offset: 0x008C */ 26 uint32_t gpio2a_p; /* Address Offset: 0x0090 */ 27 uint32_t reserved0094[11]; /* Address Offset: 0x0094 */ 28 uint32_t gpio1a_ie; /* Address Offset: 0x00C0 */ 29 uint32_t gpio1b_ie; /* Address Offset: 0x00C4 */ 30 uint32_t gpio1c_ie; /* Address Offset: 0x00C8 */ 31 uint32_t gpio1d_ie; /* Address Offset: 0x00CC */ 32 uint32_t gpio2a_ie; /* Address Offset: 0x00D0 */ 33 uint32_t reserved00d4[11]; /* Address Offset: 0x00D4 */ 34 uint32_t gpio1a_od; /* Address Offset: 0x0100 */ 35 uint32_t gpio1b_od; /* Address Offset: 0x0104 */ 36 uint32_t gpio1c_od; /* Address Offset: 0x0108 */ 37 uint32_t gpio1d_od; /* Address Offset: 0x010C */ 38 uint32_t gpio2a_od; /* Address Offset: 0x0110 */ 39 uint32_t reserved0114[11]; /* Address Offset: 0x0114 */ 40 uint32_t gpio1a_sus; /* Address Offset: 0x0140 */ 41 uint32_t gpio1b_sus; /* Address Offset: 0x0144 */ 42 uint32_t gpio1c_sus; /* Address Offset: 0x0148 */ 43 uint32_t gpio1d_sus; /* Address Offset: 0x014C */ 44 uint32_t gpio2a_sus; /* Address Offset: 0x0150 */ 45 uint32_t reserved0154[11]; /* Address Offset: 0x0154 */ 46 uint32_t gpio1a_sl; /* Address Offset: 0x0180 */ 47 uint32_t gpio1b_sl; /* Address Offset: 0x0184 */ 48 uint32_t gpio1c_sl; /* Address Offset: 0x0188 */ 49 uint32_t gpio1d_sl; /* Address Offset: 0x018C */ 50 uint32_t gpio2a_sl; /* Address Offset: 0x0190 */ 51 uint32_t reserved0194[27]; /* Address Offset: 0x0194 */ 52 uint32_t gpio1a_ds0; /* Address Offset: 0x0200 */ 53 uint32_t gpio1a_ds1; /* Address Offset: 0x0204 */ 54 uint32_t gpio1a_ds2; /* Address Offset: 0x0208 */ 55 uint32_t gpio1a_ds3; /* Address Offset: 0x020C */ 56 uint32_t gpio1b_ds0; /* Address Offset: 0x0210 */ 57 uint32_t gpio1b_ds1; /* Address Offset: 0x0214 */ 58 uint32_t gpio1b_ds2; /* Address Offset: 0x0218 */ 59 uint32_t gpio1b_ds3; /* Address Offset: 0x021C */ 60 uint32_t gpio1c_ds0; /* Address Offset: 0x0220 */ 61 uint32_t gpio1c_ds1; /* Address Offset: 0x0224 */ 62 uint32_t gpio1c_ds2; /* Address Offset: 0x0228 */ 63 uint32_t gpio1c_ds3; /* Address Offset: 0x022C */ 64 uint32_t gpio1d_ds0; /* Address Offset: 0x0230 */ 65 uint32_t gpio1d_ds1; /* Address Offset: 0x0234 */ 66 uint32_t gpio1d_ds2; /* Address Offset: 0x0238 */ 67 uint32_t gpio1d_ds3; /* Address Offset: 0x023C */ 68 uint32_t gpio2a_ds0; /* Address Offset: 0x0240 */ 69 uint32_t reserved0244[47]; /* Address Offset: 0x0244 */ 70 uint32_t io_vsel0; /* Address Offset: 0x0300 */ 71 uint32_t reserved0304[63]; /* Address Offset: 0x0304 */ 72 uint32_t mac1_io_con0; /* Address Offset: 0x0400 */ 73 uint32_t mac1_io_con1; /* Address Offset: 0x0404 */ 74 uint32_t reserved0408[62]; /* Address Offset: 0x0408 */ 75 uint32_t sdcard0_io_con; /* Address Offset: 0x0500 */ 76 uint32_t jtag_m1_con; /* Address Offset: 0x0504 */ 77 uint32_t reserved0508[16078]; /* Address Offset: 0x0508 */ 78 uint32_t gpio3a_iomux_sel_l; /* Address Offset: 0x10040 */ 79 uint32_t gpio3a_iomux_sel_h; /* Address Offset: 0x10044 */ 80 uint32_t gpio3b_iomux_sel_l; /* Address Offset: 0x10048 */ 81 uint32_t gpio3b_iomux_sel_h; /* Address Offset: 0x1004C */ 82 uint32_t gpio3c_iomux_sel_l; /* Address Offset: 0x10050 */ 83 uint32_t gpio3c_iomux_sel_h; /* Address Offset: 0x10054 */ 84 uint32_t gpio3d_iomux_sel_l; /* Address Offset: 0x10058 */ 85 uint32_t gpio3d_iomux_sel_h; /* Address Offset: 0x1005C */ 86 uint32_t gpio4a_iomux_sel_l; /* Address Offset: 0x10060 */ 87 uint32_t gpio4a_iomux_sel_h; /* Address Offset: 0x10064 */ 88 uint32_t gpio4b_iomux_sel_l; /* Address Offset: 0x10068 */ 89 uint32_t gpio4b_iomux_sel_h; /* Address Offset: 0x1006C */ 90 uint32_t reserved10070[12]; /* Address Offset: 0x10070 */ 91 uint32_t gpio3a_p; /* Address Offset: 0x100A0 */ 92 uint32_t gpio3b_p; /* Address Offset: 0x100A4 */ 93 uint32_t gpio3c_p; /* Address Offset: 0x100A8 */ 94 uint32_t gpio3d_p; /* Address Offset: 0x100AC */ 95 uint32_t gpio4a_p; /* Address Offset: 0x100B0 */ 96 uint32_t gpio4b_p; /* Address Offset: 0x100B4 */ 97 uint32_t reserved100b8[10]; /* Address Offset: 0x100B8 */ 98 uint32_t gpio3a_ie; /* Address Offset: 0x100E0 */ 99 uint32_t gpio3b_ie; /* Address Offset: 0x100E4 */ 100 uint32_t gpio3c_ie; /* Address Offset: 0x100E8 */ 101 uint32_t gpio3d_ie; /* Address Offset: 0x100EC */ 102 uint32_t gpio4a_ie; /* Address Offset: 0x100F0 */ 103 uint32_t gpio4b_ie; /* Address Offset: 0x100F4 */ 104 uint32_t reserved100f8[10]; /* Address Offset: 0x100F8 */ 105 uint32_t gpio3a_od; /* Address Offset: 0x10120 */ 106 uint32_t gpio3b_od; /* Address Offset: 0x10124 */ 107 uint32_t gpio3c_od; /* Address Offset: 0x10128 */ 108 uint32_t gpio3d_od; /* Address Offset: 0x1012C */ 109 uint32_t gpio4a_od; /* Address Offset: 0x10130 */ 110 uint32_t gpio4b_od; /* Address Offset: 0x10134 */ 111 uint32_t reserved10138[10]; /* Address Offset: 0x10138 */ 112 uint32_t gpio3a_sus; /* Address Offset: 0x10160 */ 113 uint32_t gpio3b_sus; /* Address Offset: 0x10164 */ 114 uint32_t gpio3c_sus; /* Address Offset: 0x10168 */ 115 uint32_t gpio3d_sus; /* Address Offset: 0x1016C */ 116 uint32_t gpio4a_sus; /* Address Offset: 0x10170 */ 117 uint32_t gpio4b_sus; /* Address Offset: 0x10174 */ 118 uint32_t reserved10178[10]; /* Address Offset: 0x10178 */ 119 uint32_t gpio3a_sl; /* Address Offset: 0x101A0 */ 120 uint32_t gpio3b_sl; /* Address Offset: 0x101A4 */ 121 uint32_t gpio3c_sl; /* Address Offset: 0x101A8 */ 122 uint32_t gpio3d_sl; /* Address Offset: 0x101AC */ 123 uint32_t gpio4a_sl; /* Address Offset: 0x101B0 */ 124 uint32_t gpio4b_sl; /* Address Offset: 0x101B4 */ 125 uint32_t reserved101b8[50]; /* Address Offset: 0x101B8 */ 126 uint32_t gpio3a_ds0; /* Address Offset: 0x10280 */ 127 uint32_t gpio3a_ds1; /* Address Offset: 0x10284 */ 128 uint32_t gpio3a_ds2; /* Address Offset: 0x10288 */ 129 uint32_t gpio3a_ds3; /* Address Offset: 0x1028C */ 130 uint32_t gpio3b_ds0; /* Address Offset: 0x10290 */ 131 uint32_t gpio3b_ds1; /* Address Offset: 0x10294 */ 132 uint32_t gpio3b_ds2; /* Address Offset: 0x10298 */ 133 uint32_t gpio3b_ds3; /* Address Offset: 0x1029C */ 134 uint32_t gpio3c_ds0; /* Address Offset: 0x102A0 */ 135 uint32_t gpio3c_ds1; /* Address Offset: 0x102A4 */ 136 uint32_t gpio3c_ds2; /* Address Offset: 0x102A8 */ 137 uint32_t gpio3c_ds3; /* Address Offset: 0x102AC */ 138 uint32_t gpio3d_ds0; /* Address Offset: 0x102B0 */ 139 uint32_t gpio3d_ds1; /* Address Offset: 0x102B4 */ 140 uint32_t gpio3d_ds2; /* Address Offset: 0x102B8 */ 141 uint32_t gpio3d_ds3; /* Address Offset: 0x102BC */ 142 uint32_t gpio4a_ds0; /* Address Offset: 0x102C0 */ 143 uint32_t gpio4a_ds1; /* Address Offset: 0x102C4 */ 144 uint32_t gpio4a_ds2; /* Address Offset: 0x102C8 */ 145 uint32_t gpio4a_ds3; /* Address Offset: 0x102CC */ 146 uint32_t gpio4b_ds0; /* Address Offset: 0x102D0 */ 147 uint32_t gpio4b_ds1; /* Address Offset: 0x102D4 */ 148 uint32_t gpio4b_ds2; /* Address Offset: 0x102D8 */ 149 uint32_t gpio4b_ds3; /* Address Offset: 0x102DC */ 150 uint32_t reserved102e0[8]; /* Address Offset: 0x102E0 */ 151 uint32_t io_vsel1; /* Address Offset: 0x10300 */ 152 uint32_t reserved10304[63]; /* Address Offset: 0x10304 */ 153 uint32_t mac0_io_con0; /* Address Offset: 0x10400 */ 154 uint32_t mac0_io_con1; /* Address Offset: 0x10404 */ 155 uint32_t reserved10408[62]; /* Address Offset: 0x10408 */ 156 uint32_t vo_io_con; /* Address Offset: 0x10500 */ 157 uint32_t reserved10504[35]; /* Address Offset: 0x10504 */ 158 uint32_t saradc1_con; /* Address Offset: 0x10590 */ 159 uint32_t reserved10594[16027]; /* Address Offset: 0x10594 */ 160 uint32_t gpio0a_iomux_sel_l; /* Address Offset: 0x20000 */ 161 uint32_t gpio0a_iomux_sel_h; /* Address Offset: 0x20004 */ 162 uint32_t gpio0b_iomux_sel_l; /* Address Offset: 0x20008 */ 163 uint32_t gpio0b_iomux_sel_h; /* Address Offset: 0x2000C */ 164 uint32_t gpio0c_iomux_sel_l; /* Address Offset: 0x20010 */ 165 uint32_t gpio0c_iomux_sel_h; /* Address Offset: 0x20014 */ 166 uint32_t gpio0d_iomux_sel_l; /* Address Offset: 0x20018 */ 167 uint32_t reserved2001c; /* Address Offset: 0x2001C */ 168 uint32_t gpio0a_p; /* Address Offset: 0x20020 */ 169 uint32_t gpio0b_p; /* Address Offset: 0x20024 */ 170 uint32_t gpio0c_p; /* Address Offset: 0x20028 */ 171 uint32_t gpio0d_p; /* Address Offset: 0x2002C */ 172 uint32_t gpio0a_ie; /* Address Offset: 0x20030 */ 173 uint32_t gpio0b_ie; /* Address Offset: 0x20034 */ 174 uint32_t gpio0c_ie; /* Address Offset: 0x20038 */ 175 uint32_t gpio0d_ie; /* Address Offset: 0x2003C */ 176 uint32_t gpio0a_od; /* Address Offset: 0x20040 */ 177 uint32_t gpio0b_od; /* Address Offset: 0x20044 */ 178 uint32_t gpio0c_od; /* Address Offset: 0x20048 */ 179 uint32_t gpio0d_od; /* Address Offset: 0x2004C */ 180 uint32_t gpio0a_sus; /* Address Offset: 0x20050 */ 181 uint32_t gpio0b_sus; /* Address Offset: 0x20054 */ 182 uint32_t gpio0c_sus; /* Address Offset: 0x20058 */ 183 uint32_t gpio0d_sus; /* Address Offset: 0x2005C */ 184 uint32_t gpio0a_sl; /* Address Offset: 0x20060 */ 185 uint32_t gpio0b_sl; /* Address Offset: 0x20064 */ 186 uint32_t gpio0c_sl; /* Address Offset: 0x20068 */ 187 uint32_t gpio0d_sl; /* Address Offset: 0x2006C */ 188 uint32_t gpio0a_ds0; /* Address Offset: 0x20070 */ 189 uint32_t gpio0a_ds1; /* Address Offset: 0x20074 */ 190 uint32_t gpio0a_ds2; /* Address Offset: 0x20078 */ 191 uint32_t gpio0a_ds3; /* Address Offset: 0x2007C */ 192 uint32_t gpio0b_ds0; /* Address Offset: 0x20080 */ 193 uint32_t gpio0b_ds1; /* Address Offset: 0x20084 */ 194 uint32_t gpio0b_ds2; /* Address Offset: 0x20088 */ 195 uint32_t gpio0b_ds3; /* Address Offset: 0x2008C */ 196 uint32_t gpio0c_ds0; /* Address Offset: 0x20090 */ 197 uint32_t gpio0c_ds1; /* Address Offset: 0x20094 */ 198 uint32_t gpio0c_ds2; /* Address Offset: 0x20098 */ 199 uint32_t gpio0c_ds3; /* Address Offset: 0x2009C */ 200 uint32_t gpio0d_ds0; /* Address Offset: 0x200A0 */ 201 uint32_t reserved200a4[23]; /* Address Offset: 0x200A4 */ 202 uint32_t jtag_m0_con; /* Address Offset: 0x20100 */ 203 uint32_t uart_io_con; /* Address Offset: 0x20104 */ 204 uint32_t reserved20108[16]; /* Address Offset: 0x20108 */ 205 uint32_t io_vsel2; /* Address Offset: 0x20148 */ 206 uint32_t xin_con; /* Address Offset: 0x2014C */ 207 }; 208 check_member(rk3562_ioc, xin_con, 0x2014c); 209 210 #endif 211 212