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Searched refs:sdram_params (Results 1 – 16 of 16) sorted by relevance

/OK3568_Linux_fs/u-boot/drivers/ram/rockchip/
H A Dsdram_rk3399.c70 struct rk3399_sdram_params sdram_params;
140 const struct rk3399_sdram_params *sdram_params) in set_memory_map() argument
143 &sdram_params->ch[channel]; in set_memory_map()
179 if (sdram_params->base.dramtype == LPDDR4) { in set_memory_map()
191 sdram_params->base.dramtype == DDR3) in set_memory_map()
196 struct rk3399_sdram_params *sdram_params, u32 rd_vref, in phy_io_config() argument
215 denali_phy = sdram_params->phy_regs.denali_phy; in phy_io_config()
216 denali_ctl = sdram_params->pctl_regs.denali_ctl; in phy_io_config()
220 if (sdram_params->base.dramtype == LPDDR4) { in phy_io_config()
237 } else if (sdram_params->base.dramtype == LPDDR3) { in phy_io_config()
[all …]
H A Dsdram_px30.c121 struct px30_sdram_params *sdram_params) in rkclk_configure_ddr() argument
124 rkclk_set_dpll(dram, sdram_params->base.ddr_freq * MHz * 2); in rkclk_configure_ddr()
132 static unsigned int calculate_ddrconfig(struct px30_sdram_params *sdram_params) in calculate_ddrconfig() argument
134 struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; in calculate_ddrconfig()
144 if (sdram_params->base.dramtype == DDR4) { in calculate_ddrconfig()
170 struct px30_sdram_params *sdram_params) in set_ctl_address_map() argument
172 struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; in set_ctl_address_map()
177 if (sdram_params->base.dramtype == DDR4) in set_ctl_address_map()
194 if (sdram_params->base.dramtype == DDR4) { in set_ctl_address_map()
216 if ((sdram_params->base.dramtype == LPDDR3 || in set_ctl_address_map()
[all …]
H A Dsdram_rk3288.c243 struct rk3288_sdram_params *sdram_params, in pctl_cfg() argument
248 burstlen = (sdram_params->base.noc_timing >> 18) & 0x7; in pctl_cfg()
249 copy_to_reg(&pctl->togcnt1u, &sdram_params->pctl_timing.togcnt1u, in pctl_cfg()
250 sizeof(sdram_params->pctl_timing)); in pctl_cfg()
251 switch (sdram_params->base.dramtype) { in pctl_cfg()
253 writel(sdram_params->pctl_timing.tcl - 1, in pctl_cfg()
255 writel(sdram_params->pctl_timing.tcwl, in pctl_cfg()
266 sdram_params->base.odt); in pctl_cfg()
269 if (sdram_params->phy_timing.mr[1] & DDR3_DLL_DISABLE) { in pctl_cfg()
270 writel(sdram_params->pctl_timing.tcl - 3, in pctl_cfg()
[all …]
H A Dsdram_rk3188.c230 struct rk3188_sdram_params *sdram_params, in pctl_cfg() argument
233 copy_to_reg(&pctl->togcnt1u, &sdram_params->pctl_timing.togcnt1u, in pctl_cfg()
234 sizeof(sdram_params->pctl_timing)); in pctl_cfg()
235 switch (sdram_params->base.dramtype) { in pctl_cfg()
237 if (sdram_params->phy_timing.mr[1] & DDR3_DLL_DISABLE) { in pctl_cfg()
238 writel(sdram_params->pctl_timing.tcl - 3, in pctl_cfg()
241 writel(sdram_params->pctl_timing.tcl - 2, in pctl_cfg()
244 writel(sdram_params->pctl_timing.tcwl - 1, in pctl_cfg()
259 struct rk3188_sdram_params *sdram_params) in phy_cfg() argument
263 uint ddr_freq_mhz = sdram_params->base.ddr_freq / 1000000; in phy_cfg()
[all …]
H A Dsdram_rk3328.c45 struct rk3328_sdram_params sdram_params;
121 struct rk3328_sdram_params *sdram_params) in rkclk_configure_ddr() argument
129 rkclk_set_dpll(dram, sdram_params->base.ddr_freq * MHZ * 2); in rkclk_configure_ddr()
138 struct rk3328_sdram_params *sdram_params) in calculate_ddrconfig() argument
140 struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; in calculate_ddrconfig()
154 if (sdram_params->base.dramtype == DDR4) { in calculate_ddrconfig()
220 struct rk3328_sdram_params *sdram_params) in set_ctl_address_map() argument
222 struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; in set_ctl_address_map()
227 if (sdram_params->base.dramtype == LPDDR3 && cap_info->row_3_4) in set_ctl_address_map()
229 if (sdram_params->base.dramtype == DDR4 && cap_info->bw == 0x1) in set_ctl_address_map()
[all …]
H A Dsdram_rv1126.c384 struct rv1126_sdram_params *sdram_params) in rkclk_configure_ddr() argument
387 rkclk_set_dpll(dram, sdram_params->base.ddr_freq * MHZ / 2); in rkclk_configure_ddr()
391 calculate_ddrconfig(struct rv1126_sdram_params *sdram_params) in calculate_ddrconfig() argument
393 struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; in calculate_ddrconfig()
409 if (sdram_params->base.dramtype == DDR4) { in calculate_ddrconfig()
480 if (sdram_params->base.dramtype == DDR4) { in calculate_ddrconfig()
518 struct rv1126_sdram_params *sdram_params) in set_ctl_address_map() argument
520 struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; in set_ctl_address_map()
526 if (sdram_params->base.dramtype == DDR4) { in set_ctl_address_map()
549 if (sdram_params->base.dramtype == LPDDR3 && cap_info->row_3_4) in set_ctl_address_map()
[all …]
H A Dsdram_rk322x.c163 struct rk322x_sdram_params *sdram_params) in memory_init() argument
166 u32 dramtype = sdram_params->base.dramtype; in memory_init()
174 (sdram_params->phy_timing.mr[2] & CMD_ADDR_MASK) << in memory_init()
179 (sdram_params->phy_timing.mr[3] & CMD_ADDR_MASK) << in memory_init()
184 (sdram_params->phy_timing.mr[1] & CMD_ADDR_MASK) << in memory_init()
189 ((sdram_params->phy_timing.mr[0] | in memory_init()
212 (sdram_params->phy_timing.mr[1] & in memory_init()
216 (sdram_params->phy_timing.mr[2] & in memory_init()
220 (sdram_params->phy_timing.mr[3] & in memory_init()
225 (sdram_params->phy_timing.mr11 & in memory_init()
[all …]
H A Dsdram_rv1108.c25 struct sdram_params params;
39 struct sdram_params *params_priv) in rkdclk_init()
97 struct sdram_params *params_priv) in pctl_cfg_grf()
104 struct sdram_params *params_priv) in ddr_msch_cfg()
117 void ddr_msch_cfg_rbc(struct sdram_params *params_priv, in ddr_msch_cfg_rbc()
134 struct sdram_params *params_priv) in set_ds_odt()
187 struct sdram_params *params_priv) in modify_data_training()
202 struct sdram_params *params_priv) in enable_low_power()
236 struct sdram_params *params = (void *)dtplat->rockchip_sdram_params; in sdram_init()
246 struct sdram_params *params = (void *)info->platdata; in sdram_init()
H A Dsdram_rk3308.c40 struct sdram_params sdram_configs[] = {
108 struct sdram_params *params_priv) in rkdclk_init()
452 struct sdram_params *params_priv) in pctl_cfg_grf()
464 struct sdram_params *params_priv) in ddr_msch_cfg()
472 void ddr_msch_cfg_rbc(struct sdram_params *params_priv, in ddr_msch_cfg_rbc()
514 struct sdram_params *params_priv) in set_ds_odt()
581 struct sdram_params *params_priv) in enable_ddr_standby()
686 struct sdram_params *params_priv) in modify_sdram_params()
782 struct sdram_params *params_priv) in modify_data_training()
826 struct sdram_params *params_priv) in enable_low_power()
[all …]
H A Dsdram_rv1108_pctl_phy.c112 struct sdram_params *params_priv) in memory_init()
261 struct sdram_params *params_priv) in pctl_cfg()
372 struct sdram_params *params_priv) in phy_cfg()
406 struct sdram_params *params_priv) in dram_cfg_rbc()
450 struct sdram_params *params_priv) in sdram_detect()
524 struct sdram_params *params_priv) in sdram_all_config()
611 struct sdram_params *params_priv) in rv1108_sdram_init()
/OK3568_Linux_fs/u-boot/arch/arm/mach-rockchip/rk3066/
H A Dsdram_rk3066.c220 struct rk3066_sdram_params *sdram_params, in pctl_cfg() argument
223 copy_to_reg(&pctl->togcnt1u, &sdram_params->pctl_timing.togcnt1u, in pctl_cfg()
224 sizeof(sdram_params->pctl_timing)); in pctl_cfg()
225 switch (sdram_params->base.dramtype) { in pctl_cfg()
227 if (sdram_params->phy_timing.mr[1] & DDR3_DLL_DISABLE) { in pctl_cfg()
228 writel(sdram_params->pctl_timing.tcl - 3, in pctl_cfg()
231 writel(sdram_params->pctl_timing.tcl - 2, in pctl_cfg()
234 writel(sdram_params->pctl_timing.tcwl - 1, in pctl_cfg()
248 struct rk3066_sdram_params *sdram_params) in phy_cfg() argument
252 uint ddr_freq_mhz = sdram_params->base.ddr_freq / 1000000; in phy_cfg()
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dsdram_rv1108.h52 struct sdram_params { struct
61 struct sdram_params *params_priv); argument
63 struct sdram_params *params_priv);
64 void ddr_msch_cfg_rbc(struct sdram_params *params_priv,
74 struct sdram_params *params_priv);
77 struct sdram_params *params_priv);
80 struct sdram_params *params_priv);
82 struct sdram_params *params_priv);
85 struct sdram_params *params_priv);
H A Dsdram_rk3308.h85 struct sdram_params { struct
107 struct sdram_params *params_priv); argument
110 struct sdram_params *params_priv);
111 void ddr_msch_cfg_rbc(struct sdram_params *params_priv,
121 struct sdram_params *params_priv);
125 struct sdram_params *params_priv);
129 struct sdram_params *params_priv);
131 struct sdram_params *params_priv);
134 struct sdram_params *params_priv);
/OK3568_Linux_fs/kernel/drivers/cpufreq/
H A Dsa1110-cpufreq.c32 struct sdram_params { struct
49 static struct sdram_params sdram_tbl[] __initdata = { argument
115 static struct sdram_params sdram_params; variable
144 struct sdram_params *sdram) in sdram_calculate_timing()
213 sdram_update_refresh(u_int cpu_khz, struct sdram_params *sdram) in sdram_update_refresh()
231 struct sdram_params *sdram = &sdram_params; in sa1110_target()
322 static struct sdram_params *sa1110_find_sdram(const char *name) in sa1110_find_sdram()
324 struct sdram_params *sdram; in sa1110_find_sdram()
338 struct sdram_params *sdram; in sa1110_clk_init()
364 memcpy(&sdram_params, sdram, sizeof(sdram_params)); in sa1110_clk_init()
/OK3568_Linux_fs/u-boot/arch/arm/mach-tegra/tegra20/
H A Dwarmboot.c125 struct sdram_params sdram; in warmboot_save_sdram_params()
143 (char *)((struct sdram_params *)SDRAM_PARAMS_BASE + ram_code), in warmboot_save_sdram_params()
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-tegra20/
H A Dsdram_param.h28 struct sdram_params { struct