1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2010, 2011 3*4882a593Smuzhiyun * NVIDIA Corporation <www.nvidia.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _SDRAM_PARAM_H_ 9*4882a593Smuzhiyun #define _SDRAM_PARAM_H_ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* 12*4882a593Smuzhiyun * Defines the number of 32-bit words provided in each set of SDRAM parameters 13*4882a593Smuzhiyun * for arbitration configuration data. 14*4882a593Smuzhiyun */ 15*4882a593Smuzhiyun #define BCT_SDRAM_ARB_CONFIG_WORDS 27 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun enum memory_type { 18*4882a593Smuzhiyun MEMORY_TYPE_NONE = 0, 19*4882a593Smuzhiyun MEMORY_TYPE_DDR, 20*4882a593Smuzhiyun MEMORY_TYPE_LPDDR, 21*4882a593Smuzhiyun MEMORY_TYPE_DDR2, 22*4882a593Smuzhiyun MEMORY_TYPE_LPDDR2, 23*4882a593Smuzhiyun MEMORY_TYPE_NUM, 24*4882a593Smuzhiyun MEMORY_TYPE_FORCE32 = 0x7FFFFFFF 25*4882a593Smuzhiyun }; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* Defines the SDRAM parameter structure */ 28*4882a593Smuzhiyun struct sdram_params { 29*4882a593Smuzhiyun enum memory_type memory_type; 30*4882a593Smuzhiyun u32 pllm_charge_pump_setup_control; 31*4882a593Smuzhiyun u32 pllm_loop_filter_setup_control; 32*4882a593Smuzhiyun u32 pllm_input_divider; 33*4882a593Smuzhiyun u32 pllm_feedback_divider; 34*4882a593Smuzhiyun u32 pllm_post_divider; 35*4882a593Smuzhiyun u32 pllm_stable_time; 36*4882a593Smuzhiyun u32 emc_clock_divider; 37*4882a593Smuzhiyun u32 emc_auto_cal_interval; 38*4882a593Smuzhiyun u32 emc_auto_cal_config; 39*4882a593Smuzhiyun u32 emc_auto_cal_wait; 40*4882a593Smuzhiyun u32 emc_pin_program_wait; 41*4882a593Smuzhiyun u32 emc_rc; 42*4882a593Smuzhiyun u32 emc_rfc; 43*4882a593Smuzhiyun u32 emc_ras; 44*4882a593Smuzhiyun u32 emc_rp; 45*4882a593Smuzhiyun u32 emc_r2w; 46*4882a593Smuzhiyun u32 emc_w2r; 47*4882a593Smuzhiyun u32 emc_r2p; 48*4882a593Smuzhiyun u32 emc_w2p; 49*4882a593Smuzhiyun u32 emc_rd_rcd; 50*4882a593Smuzhiyun u32 emc_wr_rcd; 51*4882a593Smuzhiyun u32 emc_rrd; 52*4882a593Smuzhiyun u32 emc_rext; 53*4882a593Smuzhiyun u32 emc_wdv; 54*4882a593Smuzhiyun u32 emc_quse; 55*4882a593Smuzhiyun u32 emc_qrst; 56*4882a593Smuzhiyun u32 emc_qsafe; 57*4882a593Smuzhiyun u32 emc_rdv; 58*4882a593Smuzhiyun u32 emc_refresh; 59*4882a593Smuzhiyun u32 emc_burst_refresh_num; 60*4882a593Smuzhiyun u32 emc_pdex2wr; 61*4882a593Smuzhiyun u32 emc_pdex2rd; 62*4882a593Smuzhiyun u32 emc_pchg2pden; 63*4882a593Smuzhiyun u32 emc_act2pden; 64*4882a593Smuzhiyun u32 emc_ar2pden; 65*4882a593Smuzhiyun u32 emc_rw2pden; 66*4882a593Smuzhiyun u32 emc_txsr; 67*4882a593Smuzhiyun u32 emc_tcke; 68*4882a593Smuzhiyun u32 emc_tfaw; 69*4882a593Smuzhiyun u32 emc_trpab; 70*4882a593Smuzhiyun u32 emc_tclkstable; 71*4882a593Smuzhiyun u32 emc_tclkstop; 72*4882a593Smuzhiyun u32 emc_trefbw; 73*4882a593Smuzhiyun u32 emc_quseextra; 74*4882a593Smuzhiyun u32 emc_fbioc_fg1; 75*4882a593Smuzhiyun u32 emc_fbio_dqsib_dly; 76*4882a593Smuzhiyun u32 emc_fbio_dqsib_dly_msb; 77*4882a593Smuzhiyun u32 emc_fbio_quse_dly; 78*4882a593Smuzhiyun u32 emc_fbio_quse_dly_msb; 79*4882a593Smuzhiyun u32 emc_fbio_cfg5; 80*4882a593Smuzhiyun u32 emc_fbio_cfg6; 81*4882a593Smuzhiyun u32 emc_fbio_spare; 82*4882a593Smuzhiyun u32 emc_mrs; 83*4882a593Smuzhiyun u32 emc_emrs; 84*4882a593Smuzhiyun u32 emc_mrw1; 85*4882a593Smuzhiyun u32 emc_mrw2; 86*4882a593Smuzhiyun u32 emc_mrw3; 87*4882a593Smuzhiyun u32 emc_mrw_reset_command; 88*4882a593Smuzhiyun u32 emc_mrw_reset_init_wait; 89*4882a593Smuzhiyun u32 emc_adr_cfg; 90*4882a593Smuzhiyun u32 emc_adr_cfg1; 91*4882a593Smuzhiyun u32 emc_emem_cfg; 92*4882a593Smuzhiyun u32 emc_low_latency_config; 93*4882a593Smuzhiyun u32 emc_cfg; 94*4882a593Smuzhiyun u32 emc_cfg2; 95*4882a593Smuzhiyun u32 emc_dbg; 96*4882a593Smuzhiyun u32 ahb_arbitration_xbar_ctrl; 97*4882a593Smuzhiyun u32 emc_cfg_dig_dll; 98*4882a593Smuzhiyun u32 emc_dll_xform_dqs; 99*4882a593Smuzhiyun u32 emc_dll_xform_quse; 100*4882a593Smuzhiyun u32 warm_boot_wait; 101*4882a593Smuzhiyun u32 emc_ctt_term_ctrl; 102*4882a593Smuzhiyun u32 emc_odt_write; 103*4882a593Smuzhiyun u32 emc_odt_read; 104*4882a593Smuzhiyun u32 emc_zcal_ref_cnt; 105*4882a593Smuzhiyun u32 emc_zcal_wait_cnt; 106*4882a593Smuzhiyun u32 emc_zcal_mrw_cmd; 107*4882a593Smuzhiyun u32 emc_mrs_reset_dll; 108*4882a593Smuzhiyun u32 emc_mrw_zq_init_dev0; 109*4882a593Smuzhiyun u32 emc_mrw_zq_init_dev1; 110*4882a593Smuzhiyun u32 emc_mrw_zq_init_wait; 111*4882a593Smuzhiyun u32 emc_mrs_reset_dll_wait; 112*4882a593Smuzhiyun u32 emc_emrs_emr2; 113*4882a593Smuzhiyun u32 emc_emrs_emr3; 114*4882a593Smuzhiyun u32 emc_emrs_ddr2_dll_enable; 115*4882a593Smuzhiyun u32 emc_mrs_ddr2_dll_reset; 116*4882a593Smuzhiyun u32 emc_emrs_ddr2_ocd_calib; 117*4882a593Smuzhiyun u32 emc_edr2_wait; 118*4882a593Smuzhiyun u32 emc_cfg_clktrim0; 119*4882a593Smuzhiyun u32 emc_cfg_clktrim1; 120*4882a593Smuzhiyun u32 emc_cfg_clktrim2; 121*4882a593Smuzhiyun u32 pmc_ddr_pwr; 122*4882a593Smuzhiyun u32 apb_misc_gp_xm2cfga_padctrl; 123*4882a593Smuzhiyun u32 apb_misc_gp_xm2cfgc_padctrl; 124*4882a593Smuzhiyun u32 apb_misc_gp_xm2cfgc_padctrl2; 125*4882a593Smuzhiyun u32 apb_misc_gp_xm2cfgd_padctrl; 126*4882a593Smuzhiyun u32 apb_misc_gp_xm2cfgd_padctrl2; 127*4882a593Smuzhiyun u32 apb_misc_gp_xm2clkcfg_padctrl; 128*4882a593Smuzhiyun u32 apb_misc_gp_xm2comp_padctrl; 129*4882a593Smuzhiyun u32 apb_misc_gp_xm2vttgen_padctrl; 130*4882a593Smuzhiyun u32 arbitration_config[BCT_SDRAM_ARB_CONFIG_WORDS]; 131*4882a593Smuzhiyun }; 132*4882a593Smuzhiyun #endif 133