Lines Matching refs:sdram_params
70 struct rk3399_sdram_params sdram_params;
140 const struct rk3399_sdram_params *sdram_params) in set_memory_map() argument
143 &sdram_params->ch[channel]; in set_memory_map()
179 if (sdram_params->base.dramtype == LPDDR4) { in set_memory_map()
191 sdram_params->base.dramtype == DDR3) in set_memory_map()
196 struct rk3399_sdram_params *sdram_params, u32 rd_vref, in phy_io_config() argument
215 denali_phy = sdram_params->phy_regs.denali_phy; in phy_io_config()
216 denali_ctl = sdram_params->pctl_regs.denali_ctl; in phy_io_config()
220 if (sdram_params->base.dramtype == LPDDR4) { in phy_io_config()
237 } else if (sdram_params->base.dramtype == LPDDR3) { in phy_io_config()
239 if (sdram_params->base.odt == 1) { in phy_io_config()
287 } else if (sdram_params->base.dramtype == DDR3) { in phy_io_config()
327 if (sdram_params->base.dramtype == LPDDR4) { in phy_io_config()
350 if (sdram_params->base.dramtype == LPDDR4) { in phy_io_config()
373 if (sdram_params->base.ddr_freq < 400 * MHz) in phy_io_config()
375 else if (sdram_params->base.ddr_freq < 800 * MHz) in phy_io_config()
377 else if (sdram_params->base.ddr_freq < 1200 * MHz) in phy_io_config()
399 if (sdram_params->base.dramtype == LPDDR4) { in phy_io_config()
510 static struct io_setting *get_io_set(struct rk3399_sdram_params *sdram_params, in get_io_set() argument
519 if (io->mhz >= sdram_params->base.ddr_freq && in get_io_set()
523 if (io->mhz >= sdram_params->base.ddr_freq) in get_io_set()
536 struct rk3399_sdram_params *sdram_params, u32 b_reg, in set_ds_odt() argument
555 denali_phy = sdram_params->phy_regs.denali_phy; in set_ds_odt()
556 denali_ctl = sdram_params->pctl_regs.denali_ctl; in set_ds_odt()
559 if (sdram_params->base.dramtype == LPDDR4) { in set_ds_odt()
560 io = get_io_set(sdram_params, mr5); in set_ds_odt()
605 } else if (sdram_params->base.dramtype == LPDDR3) { in set_ds_odt()
637 if (sdram_params->base.dramtype == LPDDR4) { in set_ds_odt()
638 if (sdram_params->base.odt == 1) { in set_ds_odt()
646 tsel_rd_en = sdram_params->base.odt; in set_ds_odt()
693 if (sdram_params->base.dramtype == LPDDR4) { in set_ds_odt()
767 if (sdram_params->base.dramtype == LPDDR4) in set_ds_odt()
768 phy_io_config(chan, sdram_params, io->rd_vref, b_reg, channel); in set_ds_odt()
770 phy_io_config(chan, sdram_params, 0, b_reg, channel); in set_ds_odt()
774 struct rk3399_sdram_params *sdram_params, in pctl_start() argument
864 if (sdram_params->base.dramtype == LPDDR4) in pctl_start()
866 sdram_params->phy_regs.denali_phy[937] & in pctl_start()
877 struct rk3399_sdram_params *sdram_params) in get_phy_index_params() argument
880 return sdram_params; in get_phy_index_params()
895 struct rk3399_sdram_params *sdram_params, u32 ctl_fn, in set_lp4_dq_odt() argument
907 denali_pi = sdram_params->pi_regs.denali_pi; in set_lp4_dq_odt()
908 denali_ctl = sdram_params->pctl_regs.denali_ctl; in set_lp4_dq_odt()
910 io = get_io_set(sdram_params, mr5); in set_lp4_dq_odt()
954 struct rk3399_sdram_params *sdram_params, u32 ctl_fn, in set_lp4_ca_odt() argument
966 denali_pi = sdram_params->pi_regs.denali_pi; in set_lp4_ca_odt()
967 denali_ctl = sdram_params->pctl_regs.denali_ctl; in set_lp4_ca_odt()
969 io = get_io_set(sdram_params, mr5); in set_lp4_ca_odt()
1013 struct rk3399_sdram_params *sdram_params, u32 ctl_fn, in set_lp4_MR3() argument
1025 denali_pi = sdram_params->pi_regs.denali_pi; in set_lp4_MR3()
1026 denali_ctl = sdram_params->pctl_regs.denali_ctl; in set_lp4_MR3()
1028 io = get_io_set(sdram_params, mr5); in set_lp4_MR3()
1071 struct rk3399_sdram_params *sdram_params, u32 ctl_fn, in set_lp4_MR12() argument
1083 denali_pi = sdram_params->pi_regs.denali_pi; in set_lp4_MR12()
1084 denali_ctl = sdram_params->pctl_regs.denali_ctl; in set_lp4_MR12()
1086 io = get_io_set(sdram_params, mr5); in set_lp4_MR12()
1131 struct rk3399_sdram_params *sdram_params, u32 ctl_fn, in set_lp4_MR14() argument
1143 denali_pi = sdram_params->pi_regs.denali_pi; in set_lp4_MR14()
1144 denali_ctl = sdram_params->pctl_regs.denali_ctl; in set_lp4_MR14()
1146 io = get_io_set(sdram_params, mr5); in set_lp4_MR14()
1186 struct rk3399_sdram_params *sdram_params) in modify_param() argument
1193 denali_ctl_params = sdram_params->pctl_regs.denali_ctl; in modify_param()
1194 denali_pi_params = sdram_params->pi_regs.denali_pi; in modify_param()
1195 denali_phy_params = sdram_params->phy_regs.denali_phy; in modify_param()
1197 if (sdram_params->base.dramtype == LPDDR4) { in modify_param()
1198 set_lp4_dq_odt(chan, sdram_params, 2, 1, 0, 0, 0); in modify_param()
1199 set_lp4_ca_odt(chan, sdram_params, 2, 1, 0, 0, 0); in modify_param()
1200 set_lp4_MR3(chan, sdram_params, 2, 0, 0, 0); in modify_param()
1201 set_lp4_MR12(chan, sdram_params, 2, 0, 0, 0); in modify_param()
1202 set_lp4_MR14(chan, sdram_params, 2, 0, 0, 0); in modify_param()
1203 params = get_phy_index_params(0, sdram_params); in modify_param()
1231 params = get_phy_index_params(0, sdram_params); in modify_param()
1242 struct rk3399_sdram_params *sdram_params) in pctl_cfg() argument
1247 const u32 *params_ctl = sdram_params->pctl_regs.denali_ctl; in pctl_cfg()
1248 const u32 *params_phy = sdram_params->phy_regs.denali_phy; in pctl_cfg()
1253 modify_param(chan, sdram_params); in pctl_cfg()
1268 if (sdram_params->base.dramtype == LPDDR4 && channel == 1) { in pctl_cfg()
1269 tmp = ((1000000 * (sdram_params->base.ddr_freq / MHz) + 999) / in pctl_cfg()
1275 sdram_copy_to_reg(denali_pi, &sdram_params->pi_regs.denali_pi[0], in pctl_cfg()
1278 set_memory_map(chan, channel, sdram_params); in pctl_cfg()
1280 writel(sdram_params->phy_regs.denali_phy[910], &denali_phy[910]); in pctl_cfg()
1281 writel(sdram_params->phy_regs.denali_phy[911], &denali_phy[911]); in pctl_cfg()
1282 writel(sdram_params->phy_regs.denali_phy[912], &denali_phy[912]); in pctl_cfg()
1284 if (sdram_params->base.dramtype == LPDDR4) { in pctl_cfg()
1285 writel(sdram_params->phy_regs.denali_phy[898], in pctl_cfg()
1287 writel(sdram_params->phy_regs.denali_phy[919], in pctl_cfg()
1304 if (sdram_params->base.dramtype != LPDDR4) { in pctl_cfg()
1333 if (sdram_params->base.dramtype == LPDDR4) in pctl_cfg()
1334 params = get_phy_index_params(1, sdram_params); in pctl_cfg()
1336 params = get_phy_index_params(0, sdram_params); in pctl_cfg()
1342 writel(sdram_params->phy_regs.denali_phy[83] + (0x10 << 16), in pctl_cfg()
1344 writel(sdram_params->phy_regs.denali_phy[84] + (0x10 << 8), in pctl_cfg()
1346 writel(sdram_params->phy_regs.denali_phy[211] + (0x10 << 16), in pctl_cfg()
1348 writel(sdram_params->phy_regs.denali_phy[212] + (0x10 << 8), in pctl_cfg()
1350 writel(sdram_params->phy_regs.denali_phy[339] + (0x10 << 16), in pctl_cfg()
1352 writel(sdram_params->phy_regs.denali_phy[340] + (0x10 << 8), in pctl_cfg()
1354 writel(sdram_params->phy_regs.denali_phy[467] + (0x10 << 16), in pctl_cfg()
1356 writel(sdram_params->phy_regs.denali_phy[468] + (0x10 << 8), in pctl_cfg()
1359 if (sdram_params->base.dramtype == LPDDR4) { in pctl_cfg()
1430 const struct rk3399_sdram_params *sdram_params) in data_training_ca() argument
1436 u32 rank = sdram_params->ch[channel].cap_info.rank; in data_training_ca()
1442 if (sdram_params->base.dramtype == LPDDR4) in data_training_ca()
1491 const struct rk3399_sdram_params *sdram_params) in data_training_wl() argument
1497 u32 rank = sdram_params->ch[channel].cap_info.rank; in data_training_wl()
1550 const struct rk3399_sdram_params *sdram_params) in data_training_rg() argument
1556 u32 rank = sdram_params->ch[channel].cap_info.rank; in data_training_rg()
1610 const struct rk3399_sdram_params *sdram_params) in data_training_rl() argument
1614 u32 rank = sdram_params->ch[channel].cap_info.rank; in data_training_rl()
1654 const struct rk3399_sdram_params *sdram_params) in data_training_wdql() argument
1658 u32 rank = sdram_params->ch[channel].cap_info.rank; in data_training_wdql()
1664 if (sdram_params->base.dramtype == LPDDR4) in data_training_wdql()
1706 const struct rk3399_sdram_params *sdram_params, in data_training() argument
1716 if (sdram_params->base.dramtype == LPDDR4) { in data_training()
1720 } else if (sdram_params->base.dramtype == LPDDR3) { in data_training()
1723 } else if (sdram_params->base.dramtype == DDR3) { in data_training()
1732 ret = data_training_ca(chan, channel, sdram_params); in data_training()
1739 ret = data_training_wl(chan, channel, sdram_params); in data_training()
1746 ret = data_training_rg(chan, channel, sdram_params); in data_training()
1753 ret = data_training_rl(chan, channel, sdram_params); in data_training()
1760 ret = data_training_wdql(chan, channel, sdram_params); in data_training()
1773 const struct rk3399_sdram_params *sdram_params, in set_ddrconfig() argument
1781 cs0_cap = (1 << (sdram_params->ch[channel].cap_info.cs0_row in set_ddrconfig()
1782 + sdram_params->ch[channel].cap_info.col in set_ddrconfig()
1783 + sdram_params->ch[channel].cap_info.bk in set_ddrconfig()
1784 + sdram_params->ch[channel].cap_info.bw - 20)); in set_ddrconfig()
1785 if (sdram_params->ch[channel].cap_info.rank > 1) in set_ddrconfig()
1786 cs1_cap = cs0_cap >> (sdram_params->ch[channel].cap_info.cs0_row in set_ddrconfig()
1787 - sdram_params->ch[channel].cap_info.cs1_row); in set_ddrconfig()
1788 if (sdram_params->ch[channel].cap_info.row_3_4) { in set_ddrconfig()
1814 struct rk3399_sdram_params *sdram_params) in dram_all_config() argument
1821 (idx < sdram_params->base.num_channels) && (channel < 2); in dram_all_config()
1826 if (sdram_params->ch[channel].cap_info.col == 0) in dram_all_config()
1829 sdram_org_config(&sdram_params->ch[channel].cap_info, in dram_all_config()
1830 &sdram_params->base, &sys_reg2, in dram_all_config()
1833 noc_timing = &sdram_params->ch[channel].noc_timings; in dram_all_config()
1837 if (sdram_params->ch[channel].cap_info.rank == 1) in dram_all_config()
1845 sdram_params->base.stride << 10); in dram_all_config()
1855 const struct rk3399_sdram_params *sdram_params) in switch_to_phy_index1() argument
1859 u32 ch_count = sdram_params->base.num_channels; in switch_to_phy_index1()
1889 sdram_params, PI_FULL_TRAINING); in switch_to_phy_index1()
1918 static u32 calculate_ddrconfig(struct rk3399_sdram_params *sdram_params, in calculate_ddrconfig() argument
1922 unsigned int cs0_row = sdram_params->ch[channel].cap_info.cs0_row; in calculate_ddrconfig()
1923 unsigned int col = sdram_params->ch[channel].cap_info.col; in calculate_ddrconfig()
1924 unsigned int bw = sdram_params->ch[channel].cap_info.bw; in calculate_ddrconfig()
1941 static unsigned char calculate_stride(struct rk3399_sdram_params *sdram_params) in calculate_stride() argument
1956 &sdram_params->ch[channel].cap_info; in calculate_stride()
1975 if (sdram_params->base.num_channels == 1) { in calculate_stride()
2108 struct rk3399_sdram_params *sdram_params, in set_cap_relate_config() argument
2115 if (sdram_params->base.dramtype == LPDDR3) { in set_cap_relate_config()
2116 tmp = (8 << sdram_params->ch[channel].cap_info.bw) / in set_cap_relate_config()
2117 (8 << sdram_params->ch[channel].cap_info.dbw); in set_cap_relate_config()
2126 noc_timing = &sdram_params->ch[channel].noc_timings; in set_cap_relate_config()
2131 if (sdram_params->ch[channel].cap_info.bw == 16 && in set_cap_relate_config()
2141 static void clear_channel_params(struct rk3399_sdram_params *sdram_params, in clear_channel_params() argument
2144 sdram_params->ch[channel].cap_info.rank = 0; in clear_channel_params()
2145 sdram_params->ch[channel].cap_info.col = 0; in clear_channel_params()
2146 sdram_params->ch[channel].cap_info.bk = 0; in clear_channel_params()
2147 sdram_params->ch[channel].cap_info.bw = 32; in clear_channel_params()
2148 sdram_params->ch[channel].cap_info.dbw = 32; in clear_channel_params()
2149 sdram_params->ch[channel].cap_info.row_3_4 = 0; in clear_channel_params()
2150 sdram_params->ch[channel].cap_info.cs0_row = 0; in clear_channel_params()
2151 sdram_params->ch[channel].cap_info.cs1_row = 0; in clear_channel_params()
2152 sdram_params->ch[channel].cap_info.ddrconfig = 0; in clear_channel_params()
2264 struct rk3399_sdram_params *sdram_params, in dram_detect_cap() argument
2268 struct sdram_cap_info *cap_info = &sdram_params->ch[channel].cap_info; in dram_detect_cap()
2279 if (sdram_params->base.dramtype != LPDDR4) { in dram_detect_cap()
2282 if (data_training(chan, channel, sdram_params, in dram_detect_cap()
2287 if (data_training(chan, channel, sdram_params, in dram_detect_cap()
2298 if (sdram_params->base.dramtype == LPDDR3) in dram_detect_cap()
2303 if (sdram_params->base.dramtype != LPDDR4) { in dram_detect_cap()
2304 if (data_training(chan, channel, sdram_params, training_flag)) { in dram_detect_cap()
2334 set_memory_map(chan, channel, sdram_params); in dram_detect_cap()
2335 ddrconfig = calculate_ddrconfig(sdram_params, channel); in dram_detect_cap()
2338 set_ddrconfig(chan, sdram_params, channel, in dram_detect_cap()
2342 sdram_detect_cs1_row(cap_info, sdram_params->base.dramtype); in dram_detect_cap()
2345 sdram_detect_dbw(cap_info, sdram_params->base.dramtype); in dram_detect_cap()
2388 struct rk3399_sdram_params *sdram_params) in read_mr_for_detect() argument
2404 if (sdram_params->ch[channel].cap_info.col == 0) { in read_mr_for_detect()
2409 cs = sdram_params->ch[channel].cap_info.rank; in read_mr_for_detect()
2410 col = sdram_params->ch[channel].cap_info.col; in read_mr_for_detect()
2411 bk = sdram_params->ch[channel].cap_info.bk; in read_mr_for_detect()
2412 bw = sdram_params->ch[channel].cap_info.bw; in read_mr_for_detect()
2413 row_3_4 = sdram_params->ch[channel].cap_info.row_3_4; in read_mr_for_detect()
2414 cs0_row = sdram_params->ch[channel].cap_info.cs0_row; in read_mr_for_detect()
2415 cs1_row = sdram_params->ch[channel].cap_info.cs1_row; in read_mr_for_detect()
2416 ddrconfig = sdram_params->ch[channel].cap_info.ddrconfig; in read_mr_for_detect()
2419 sdram_params->ch[channel].cap_info.rank = 2; in read_mr_for_detect()
2420 sdram_params->ch[channel].cap_info.col = 10; in read_mr_for_detect()
2421 sdram_params->ch[channel].cap_info.bk = 3; in read_mr_for_detect()
2422 sdram_params->ch[channel].cap_info.bw = 2; in read_mr_for_detect()
2423 sdram_params->ch[channel].cap_info.row_3_4 = 0; in read_mr_for_detect()
2424 sdram_params->ch[channel].cap_info.cs0_row = 15; in read_mr_for_detect()
2425 sdram_params->ch[channel].cap_info.cs1_row = 15; in read_mr_for_detect()
2426 sdram_params->ch[channel].cap_info.ddrconfig = 1; in read_mr_for_detect()
2428 set_memory_map(chan, channel, sdram_params); in read_mr_for_detect()
2429 sdram_params->ch[channel].cap_info.ddrconfig = in read_mr_for_detect()
2430 calculate_ddrconfig(sdram_params, channel); in read_mr_for_detect()
2431 set_ddrconfig(chan, sdram_params, channel, in read_mr_for_detect()
2432 sdram_params->ch[channel].cap_info.ddrconfig); in read_mr_for_detect()
2433 set_cap_relate_config(chan, sdram_params, channel); in read_mr_for_detect()
2435 cs0_cap = (1 << (sdram_params->ch[channel].cap_info.bw in read_mr_for_detect()
2436 + sdram_params->ch[channel].cap_info.col in read_mr_for_detect()
2437 + sdram_params->ch[channel].cap_info.bk in read_mr_for_detect()
2438 + sdram_params->ch[channel].cap_info.cs0_row)); in read_mr_for_detect()
2440 if (sdram_params->ch[channel].cap_info.row_3_4) in read_mr_for_detect()
2468 sdram_params->ch[channel].cap_info.rank = cs; in read_mr_for_detect()
2469 sdram_params->ch[channel].cap_info.col = col; in read_mr_for_detect()
2470 sdram_params->ch[channel].cap_info.bk = bk; in read_mr_for_detect()
2471 sdram_params->ch[channel].cap_info.bw = bw; in read_mr_for_detect()
2472 sdram_params->ch[channel].cap_info.row_3_4 = row_3_4; in read_mr_for_detect()
2473 sdram_params->ch[channel].cap_info.cs0_row = cs0_row; in read_mr_for_detect()
2474 sdram_params->ch[channel].cap_info.cs1_row = cs1_row; in read_mr_for_detect()
2475 sdram_params->ch[channel].cap_info.ddrconfig = ddrconfig; in read_mr_for_detect()
2481 static u32 get_phy_fn(struct rk3399_sdram_params *sdram_params, u32 ctl_fn) in get_phy_fn() argument
2485 if (sdram_params->base.dramtype == LPDDR4) in get_phy_fn()
2491 static u32 get_ctl_fn(struct rk3399_sdram_params *sdram_params, u32 phy_fn) in get_ctl_fn() argument
2495 if (sdram_params->base.dramtype == LPDDR4) in get_ctl_fn()
2502 struct rk3399_sdram_params *sdram_params, u32 fn, in dram_copy_phy_fn() argument
2822 struct rk3399_sdram_params *sdram_params, u32 fn, in dram_set_phy_fn() argument
2828 dram_copy_phy_fn(dram, sdram_params, fn, f1_sdram_params, in dram_set_phy_fn()
2833 struct rk3399_sdram_params *sdram_params, in dram_set_rate() argument
2874 if (!(sdram_params->base.dramtype == LPDDR4 && fn == 2)) { in dram_set_rate()
2876 if (!(sdram_params->ch[channel].cap_info.col)) in dram_set_rate()
2879 channel, sdram_params, in dram_set_rate()
2883 if (!(sdram_params->ch[channel].cap_info.col)) in dram_set_rate()
2926 struct rk3399_sdram_params *sdram_params) in sdram_init() argument
2928 unsigned char dramtype = sdram_params->base.dramtype; in sdram_init()
2929 unsigned int ddr_freq = sdram_params->base.ddr_freq; in sdram_init()
2947 sdram_params->ch[ch].cap_info.rank = 2; in sdram_init()
2957 pctl_cfg(chan, channel, sdram_params); in sdram_init()
2961 pctl_start(dram, sdram_params, 3); in sdram_init()
2969 sdram_params->base.dramtype); in sdram_init()
2970 sdram_params->ch[ch].cap_info.rank = rank; in sdram_init()
2971 if (sdram_params->base.dramtype == LPDDR4) { in sdram_init()
2976 sdram_params)) in sdram_init()
2985 if (sdram_params->base.dramtype == LPDDR3) in sdram_init()
2991 sdram_params, in sdram_init()
2996 sdram_params->ch[ch].cap_info.rank = rank; in sdram_init()
2999 sdram_params->base.num_channels = 0; in sdram_init()
3003 &sdram_params->ch[channel].cap_info; in sdram_init()
3006 clear_channel_params(sdram_params, 1); in sdram_init()
3009 sdram_params->base.num_channels++; in sdram_init()
3020 if (dram_detect_cap(dram, sdram_params, channel)) { in sdram_init()
3025 sdram_print_ddr_info(cap_info, &sdram_params->base, 0); in sdram_init()
3026 set_memory_map(chan, channel, sdram_params); in sdram_init()
3028 calculate_ddrconfig(sdram_params, channel); in sdram_init()
3033 set_ddrconfig(chan, sdram_params, channel, cap_info->ddrconfig); in sdram_init()
3034 set_cap_relate_config(chan, sdram_params, channel); in sdram_init()
3037 if (sdram_params->base.num_channels == 0) { in sdram_init()
3038 sdram_print_dram_type(sdram_params->base.dramtype); in sdram_init()
3039 printf(" %dMHz\n", sdram_params->base.ddr_freq); in sdram_init()
3043 sdram_params->base.stride = calculate_stride(sdram_params); in sdram_init()
3044 dram_all_config(dram, sdram_params); in sdram_init()
3046 if (sdram_params->base.dramtype != LPDDR4) in sdram_init()
3047 switch_to_phy_index1(dram, sdram_params); in sdram_init()
3049 if (sdram_params->base.dramtype == LPDDR4) { in sdram_init()
3050 g_sdram_params = sdram_params; in sdram_init()
3066 (u32 *)&plat->sdram_params, in rk3399_dmc_ofdata_to_platdata()
3067 sizeof(plat->sdram_params) / sizeof(u32)); in rk3399_dmc_ofdata_to_platdata()
3104 struct rk3399_sdram_params *params = &plat->sdram_params; in rk3399_dmc_init()