1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2018 Rockchip Electronics Co., Ltd 3*4882a593Smuzhiyun * Author: Zhihuan He <huan.he@rock-chips.com> 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _ASM_ARCH_SDRAM_RV1108_H 8*4882a593Smuzhiyun #define _ASM_ARCH_SDRAM_RV1108_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <common.h> 11*4882a593Smuzhiyun #include <ram.h> 12*4882a593Smuzhiyun #include <asm/arch/cru_rv1108.h> 13*4882a593Smuzhiyun #include <asm/arch/grf_rv1108.h> 14*4882a593Smuzhiyun #include <asm/arch/pmu_rv1108.h> 15*4882a593Smuzhiyun #include <asm/arch/sdram_rv1108_pctl_phy.h> 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define SR_IDLE 3 18*4882a593Smuzhiyun #define PD_IDLE 64 19*4882a593Smuzhiyun #define SDRAM_BEGIN_ADDR 0x60000000 20*4882a593Smuzhiyun #define SDRAM_END_ADDR 0x80000000 21*4882a593Smuzhiyun #define PATTERN (0x5aa5f00f) 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun struct rv1108_service_msch { 24*4882a593Smuzhiyun u32 id_coreid; 25*4882a593Smuzhiyun u32 id_revisionid; 26*4882a593Smuzhiyun u32 ddrconf; 27*4882a593Smuzhiyun u32 ddrtiming; 28*4882a593Smuzhiyun u32 ddrmode; 29*4882a593Smuzhiyun u32 readlatency; 30*4882a593Smuzhiyun u32 reserveds1[8]; 31*4882a593Smuzhiyun u32 activate; 32*4882a593Smuzhiyun u32 devtodev; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun enum { 36*4882a593Smuzhiyun /*memory scheduler ddrtiming*/ 37*4882a593Smuzhiyun BWRATIO_HALF_BW = 0x80000000, 38*4882a593Smuzhiyun BWRATIO_HALF_BW_DIS = 0x0, 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun struct dram_info { 42*4882a593Smuzhiyun struct rv1108_cru *cru; 43*4882a593Smuzhiyun struct rv1108_grf *grf; 44*4882a593Smuzhiyun struct rv1108_pmu *pmu; 45*4882a593Smuzhiyun struct rv1108_pmu_grf *pmu_grf; 46*4882a593Smuzhiyun struct ddr_phy *phy; 47*4882a593Smuzhiyun struct ddr_pctl *pctl; 48*4882a593Smuzhiyun struct rv1108_service_msch *service_msch; 49*4882a593Smuzhiyun struct ram_info info; 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun struct sdram_params { 53*4882a593Smuzhiyun u32 ddr_2t_en; 54*4882a593Smuzhiyun struct ddr_config ddr_config_t; 55*4882a593Smuzhiyun struct pll_div dpll_init_cfg; 56*4882a593Smuzhiyun struct ddr_timing ddr_timing_t; 57*4882a593Smuzhiyun }; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun int check_rd_gate(struct dram_info *priv); 60*4882a593Smuzhiyun void enable_low_power(struct dram_info *priv, 61*4882a593Smuzhiyun struct sdram_params *params_priv); 62*4882a593Smuzhiyun void ddr_msch_cfg(struct dram_info *priv, 63*4882a593Smuzhiyun struct sdram_params *params_priv); 64*4882a593Smuzhiyun void ddr_msch_cfg_rbc(struct sdram_params *params_priv, 65*4882a593Smuzhiyun struct dram_info *priv); 66*4882a593Smuzhiyun void ddr_msch_get_max_col(struct dram_info *priv, 67*4882a593Smuzhiyun struct ddr_schedule *sch_priv); 68*4882a593Smuzhiyun void ddr_msch_get_max_row(struct dram_info *priv, 69*4882a593Smuzhiyun struct ddr_schedule *sch_priv); 70*4882a593Smuzhiyun void ddr_phy_dqs_rx_dll_cfg(struct dram_info *priv, u32 freq); 71*4882a593Smuzhiyun void ddr_phy_skew_cfg(struct dram_info *priv); 72*4882a593Smuzhiyun void enable_ddr_io_ret(struct dram_info *priv); 73*4882a593Smuzhiyun void modify_data_training(struct dram_info *priv, 74*4882a593Smuzhiyun struct sdram_params *params_priv); 75*4882a593Smuzhiyun void move_to_config_state(struct dram_info *priv); 76*4882a593Smuzhiyun void pctl_cfg_grf(struct dram_info *priv, 77*4882a593Smuzhiyun struct sdram_params *params_priv); 78*4882a593Smuzhiyun void phy_pctrl_reset_cru(struct dram_info *priv); 79*4882a593Smuzhiyun void rkdclk_init(struct dram_info *priv, 80*4882a593Smuzhiyun struct sdram_params *params_priv); 81*4882a593Smuzhiyun int rv1108_sdram_init(struct dram_info *sdram_priv, 82*4882a593Smuzhiyun struct sdram_params *params_priv); 83*4882a593Smuzhiyun void set_bw_grf(struct dram_info *priv); 84*4882a593Smuzhiyun void set_ds_odt(struct dram_info *priv, 85*4882a593Smuzhiyun struct sdram_params *params_priv); 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun #endif 88