Lines Matching refs:sdram_params
384 struct rv1126_sdram_params *sdram_params) in rkclk_configure_ddr() argument
387 rkclk_set_dpll(dram, sdram_params->base.ddr_freq * MHZ / 2); in rkclk_configure_ddr()
391 calculate_ddrconfig(struct rv1126_sdram_params *sdram_params) in calculate_ddrconfig() argument
393 struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; in calculate_ddrconfig()
409 if (sdram_params->base.dramtype == DDR4) { in calculate_ddrconfig()
480 if (sdram_params->base.dramtype == DDR4) { in calculate_ddrconfig()
518 struct rv1126_sdram_params *sdram_params) in set_ctl_address_map() argument
520 struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; in set_ctl_address_map()
526 if (sdram_params->base.dramtype == DDR4) { in set_ctl_address_map()
549 if (sdram_params->base.dramtype == LPDDR3 && cap_info->row_3_4) in set_ctl_address_map()
551 if (sdram_params->base.dramtype == DDR4 && cap_info->bw == 0x1) in set_ctl_address_map()
878 struct rv1126_sdram_params *sdram_params, u32 dst_fsp) in set_ds_odt() argument
882 u32 dramtype = sdram_params->base.dramtype; in set_ds_odt()
894 u32 freq = sdram_params->base.ddr_freq; in set_ds_odt()
1219 struct rv1126_sdram_params *sdram_params) in sdram_cmd_dq_path_remap() argument
1222 u32 dramtype = sdram_params->base.dramtype; in sdram_cmd_dq_path_remap()
1242 struct rv1126_sdram_params *sdram_params) in phy_cfg() argument
1244 struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; in phy_cfg()
1249 sdram_cmd_dq_path_remap(dram, sdram_params); in phy_cfg()
1251 phy_pll_set(dram, sdram_params->base.ddr_freq * MHZ, 0); in phy_cfg()
1252 for (i = 0; sdram_params->phy_regs.phy[i][0] != 0xFFFFFFFF; i++) { in phy_cfg()
1253 writel(sdram_params->phy_regs.phy[i][1], in phy_cfg()
1254 phy_base + sdram_params->phy_regs.phy[i][0]); in phy_cfg()
1283 if (sdram_params->base.dramtype == LPDDR4 || in phy_cfg()
1284 sdram_params->base.dramtype == LPDDR4X) in phy_cfg()
1922 struct rv1126_sdram_params *sdram_params, u32 dst_fsp, in data_training() argument
1933 sdram_params->base.dramtype, in data_training()
1934 sdram_params->ch.cap_info.rank); in data_training()
1941 sdram_params->base.dramtype); in data_training()
1948 sdram_params->base.dramtype, in data_training()
1949 sdram_params->base.ddr_freq); in data_training()
1956 sdram_params->base.dramtype, in data_training()
1957 sdram_params->base.ddr_freq, dst_fsp); in data_training()
1967 struct rv1126_sdram_params *sdram_params) in get_wrlvl_val() argument
1978 sdram_params->base.dramtype); in get_wrlvl_val()
1980 ret = data_training(dram, 0, sdram_params, 0, WRITE_LEVELING); in get_wrlvl_val()
1981 if (sdram_params->ch.cap_info.rank == 2) in get_wrlvl_val()
1982 ret |= data_training(dram, 1, sdram_params, 0, WRITE_LEVELING); in get_wrlvl_val()
2081 struct rv1126_sdram_params *sdram_params, in high_freq_training() argument
2086 u32 dramtype = sdram_params->base.dramtype; in high_freq_training()
2094 for (j = 0; j < sdram_params->ch.cap_info.rank; j++) { in high_freq_training()
2101 (int)(sdram_params->ch.cap_info.rank * (1 << sdram_params->ch.cap_info.bw)); in high_freq_training()
2108 for (j = 0; j < sdram_params->ch.cap_info.rank; j++) in high_freq_training()
2133 ret = data_training(dram, 0, sdram_params, fsp, READ_GATE_TRAINING | in high_freq_training()
2136 rw_trn_result.fsp_mhz[fsp] = (u16)sdram_params->base.ddr_freq; in high_freq_training()
2141 if (sdram_params->ch.cap_info.rank == 2) { in high_freq_training()
2146 ret |= data_training(dram, 1, sdram_params, fsp, in high_freq_training()
2161 sdram_params->ch.cap_info.rank) * -1; in high_freq_training()
2163 min_val, min_val, sdram_params->ch.cap_info.rank); in high_freq_training()
2171 sdram_params->ch.cap_info.rank), in high_freq_training()
2173 sdram_params->ch.cap_info.rank)) * -1; in high_freq_training()
2180 min_val, min_val, sdram_params->ch.cap_info.rank); in high_freq_training()
2187 ret = data_training(dram, 0, sdram_params, 0, READ_GATE_TRAINING); in high_freq_training()
2188 if (sdram_params->ch.cap_info.rank == 2) in high_freq_training()
2189 ret |= data_training(dram, 1, sdram_params, 0, in high_freq_training()
2202 struct rv1126_sdram_params *sdram_params) in update_noc_timing() argument
2207 bw = 8 << sdram_params->ch.cap_info.bw; in update_noc_timing()
2212 sdram_params->ch.noc_timings.ddrmode.b.burstsize = 0; in update_noc_timing()
2214 sdram_params->ch.noc_timings.ddrmode.b.burstsize = 1; in update_noc_timing()
2216 sdram_params->ch.noc_timings.ddrmode.b.burstsize = 2; in update_noc_timing()
2218 sdram_params->ch.noc_timings.ddrmode.b.burstsize = 3; in update_noc_timing()
2220 sdram_params->ch.noc_timings.ddrtimingc0.b.burstpenalty = in update_noc_timing()
2223 if (sdram_params->base.dramtype == LPDDR4 || in update_noc_timing()
2224 sdram_params->base.dramtype == LPDDR4X) { in update_noc_timing()
2225 sdram_params->ch.noc_timings.ddrmode.b.mwrsize = in update_noc_timing()
2227 sdram_params->ch.noc_timings.ddrtimingc0.b.wrtomwr = in update_noc_timing()
2228 3 * sdram_params->ch.noc_timings.ddrtimingc0.b.burstpenalty; in update_noc_timing()
2231 writel(sdram_params->ch.noc_timings.ddrtiminga0.d32, in update_noc_timing()
2233 writel(sdram_params->ch.noc_timings.ddrtimingb0.d32, in update_noc_timing()
2235 writel(sdram_params->ch.noc_timings.ddrtimingc0.d32, in update_noc_timing()
2237 writel(sdram_params->ch.noc_timings.devtodev0.d32, in update_noc_timing()
2239 writel(sdram_params->ch.noc_timings.ddrmode.d32, &dram->msch->ddrmode); in update_noc_timing()
2240 writel(sdram_params->ch.noc_timings.ddr4timing.d32, in update_noc_timing()
2245 struct rv1126_sdram_params *sdram_params) in split_setup() argument
2247 struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; in split_setup()
2248 u32 dramtype = sdram_params->base.dramtype; in split_setup()
2305 struct rv1126_sdram_params *sdram_params) in dram_all_config() argument
2307 struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; in dram_all_config()
2308 u32 dram_type = sdram_params->base.dramtype; in dram_all_config()
2316 sdram_org_config(cap_info, &sdram_params->base, &sys_reg2, in dram_all_config()
2334 update_noc_timing(dram, sdram_params); in dram_all_config()
2338 struct rv1126_sdram_params *sdram_params) in enable_low_power() argument
2345 if (sdram_params->base.dramtype == DDR4) in enable_low_power()
2347 else if (sdram_params->base.dramtype == DDR3) in enable_low_power()
2369 struct rv1126_sdram_params *sdram_params) in ddr_set_atags() argument
2371 struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; in ddr_set_atags()
2372 u32 dram_type = sdram_params->base.dramtype; in ddr_set_atags()
2432 static void print_ddr_info(struct rv1126_sdram_params *sdram_params) in print_ddr_info() argument
2443 sdram_print_ddr_info(&sdram_params->ch.cap_info, in print_ddr_info()
2444 &sdram_params->base, split); in print_ddr_info()
2447 static int modify_ddr34_bw_byte_map(u8 rg_result, struct rv1126_sdram_params *sdram_params) in modify_ddr34_bw_byte_map() argument
2452 struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; in modify_ddr34_bw_byte_map()
2453 u32 dramtype = sdram_params->base.dramtype; in modify_ddr34_bw_byte_map()
2489 pctl_remodify_sdram_params(&sdram_params->pctl_regs, cap_info, dramtype); in modify_ddr34_bw_byte_map()
2496 int sdram_init_(struct dram_info *dram, struct rv1126_sdram_params *sdram_params, u32 post_init) in sdram_init_() argument
2504 rkclk_configure_ddr(dram, sdram_params); in sdram_init_()
2510 phy_cfg(dram, sdram_params); in sdram_init_()
2513 phy_pll_set(dram, sdram_params->base.ddr_freq * MHZ, 1); in sdram_init_()
2516 pctl_cfg(dram->pctl, &sdram_params->pctl_regs, in sdram_init_()
2519 if (sdram_params->ch.cap_info.bw == 2) { in sdram_init_()
2542 set_ds_odt(dram, sdram_params, 0); in sdram_init_()
2543 sdram_params->ch.cap_info.ddrconfig = calculate_ddrconfig(sdram_params); in sdram_init_()
2544 set_ctl_address_map(dram, sdram_params); in sdram_init_()
2559 if (sdram_params->base.dramtype == LPDDR3) { in sdram_init_()
2561 } else if (sdram_params->base.dramtype == LPDDR4 || in sdram_init_()
2562 sdram_params->base.dramtype == LPDDR4X) { in sdram_init_()
2580 if (sdram_params->base.dramtype == DDR3 && post_init == 0) in sdram_init_()
2582 tmp = data_training(dram, 0, sdram_params, 0, READ_GATE_TRAINING) & 0xf; in sdram_init_()
2589 if (sdram_params->base.dramtype != DDR3 || tmp == 0xf) in sdram_init_()
2593 if (sdram_params->base.dramtype == DDR3 && post_init == 0) { in sdram_init_()
2594 if (modify_ddr34_bw_byte_map((u8)tmp, sdram_params) != 0) in sdram_init_()
2598 if (sdram_params->base.dramtype == LPDDR4) { in sdram_init_()
2605 if (sdram_params->base.dramtype == LPDDR4 || in sdram_init_()
2606 sdram_params->base.dramtype == LPDDR4X) { in sdram_init_()
2613 if (post_init != 0 && sdram_params->ch.cap_info.rank == 2) { in sdram_init_()
2614 if (data_training(dram, 1, sdram_params, 0, in sdram_init_()
2621 if (sdram_params->base.dramtype == DDR4) { in sdram_init_()
2624 sdram_params->base.dramtype); in sdram_init_()
2627 dram_all_config(dram, sdram_params); in sdram_init_()
2628 enable_low_power(dram, sdram_params); in sdram_init_()
2634 struct rv1126_sdram_params *sdram_params, in dram_detect_cap() argument
2637 struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; in dram_detect_cap()
2646 u32 dram_type = sdram_params->base.dramtype; in dram_detect_cap()
2712 if (data_training(dram, 1, sdram_params, 0, READ_GATE_TRAINING) == 0) in dram_detect_cap()
2733 if (data_training(dram, 0, sdram_params, 0, READ_GATE_TRAINING) == 0) in dram_detect_cap()
2762 struct rv1126_sdram_params *sdram_params, in dram_detect_cs1_row() argument
2765 struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; in dram_detect_cs1_row()
2784 if (sdram_params->base.dramtype == DDR4) { in dram_detect_cs1_row()
2831 struct rv1126_sdram_params *sdram_params) in sdram_init_detect() argument
2833 struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; in sdram_init_detect()
2838 if (sdram_init_(dram, sdram_params, 0)) { in sdram_init_detect()
2839 if (sdram_params->base.dramtype == DDR3) { in sdram_init_detect()
2840 if (sdram_init_(dram, sdram_params, 0)) in sdram_init_detect()
2847 if (sdram_params->base.dramtype == DDR3) { in sdram_init_detect()
2854 if (dram_detect_cap(dram, sdram_params, 0) != 0) in sdram_init_detect()
2857 pctl_remodify_sdram_params(&sdram_params->pctl_regs, cap_info, in sdram_init_detect()
2858 sdram_params->base.dramtype); in sdram_init_detect()
2859 ret = sdram_init_(dram, sdram_params, 1); in sdram_init_detect()
2864 dram_detect_cs1_row(dram, sdram_params, 0); in sdram_init_detect()
2874 sdram_detect_high_row(cap_info, sdram_params->base.dramtype); in sdram_init_detect()
2875 split_setup(dram, sdram_params); in sdram_init_detect()
2937 struct rv1126_sdram_params *sdram_params, in pre_set_rate() argument
2945 u32 dramtype = sdram_params->base.dramtype; in pre_set_rate()
2950 for (j = find; sdram_params->pctl_regs.pctl[j][0] != 0xFFFFFFFF; in pre_set_rate()
2952 if (sdram_params->pctl_regs.pctl[j][0] == in pre_set_rate()
2954 writel(sdram_params->pctl_regs.pctl[j][1], in pre_set_rate()
2981 for (j = find; sdram_params->phy_regs.phy[j][0] != 0xFFFFFFFF; in pre_set_rate()
2983 if (sdram_params->phy_regs.phy[j][0] == in pre_set_rate()
2985 writel(sdram_params->phy_regs.phy[j][1], in pre_set_rate()
2994 set_ds_odt(dram, sdram_params, dst_fsp); in pre_set_rate()
3059 update_noc_timing(dram, sdram_params); in pre_set_rate()
3063 struct rv1126_sdram_params *sdram_params) in save_fsp_param() argument
3071 ddr_info = get_ddr_drv_odt_info(sdram_params->base.dramtype); in save_fsp_param()
3073 p_fsp_param->freq_mhz = sdram_params->base.ddr_freq; in save_fsp_param()
3075 if (sdram_params->base.dramtype == LPDDR4 || in save_fsp_param()
3076 sdram_params->base.dramtype == LPDDR4X) { in save_fsp_param()
3098 if (sdram_params->base.dramtype == DDR3) { in save_fsp_param()
3105 } else if (sdram_params->base.dramtype == DDR4) { in save_fsp_param()
3112 } else if (sdram_params->base.dramtype == LPDDR3) { in save_fsp_param()
3120 } else if (sdram_params->base.dramtype == LPDDR4 || in save_fsp_param()
3121 sdram_params->base.dramtype == LPDDR4X) { in save_fsp_param()
3153 sdram_params->ch.noc_timings.ddrtiminga0; in save_fsp_param()
3155 sdram_params->ch.noc_timings.ddrtimingb0; in save_fsp_param()
3157 sdram_params->ch.noc_timings.ddrtimingc0; in save_fsp_param()
3159 sdram_params->ch.noc_timings.devtodev0; in save_fsp_param()
3161 sdram_params->ch.noc_timings.ddrmode; in save_fsp_param()
3163 sdram_params->ch.noc_timings.ddr4timing; in save_fsp_param()
3165 sdram_params->ch.noc_timings.agingx0; in save_fsp_param()
3167 sdram_params->ch.noc_timings.aging0; in save_fsp_param()
3169 sdram_params->ch.noc_timings.aging1; in save_fsp_param()
3171 sdram_params->ch.noc_timings.aging2; in save_fsp_param()
3173 sdram_params->ch.noc_timings.aging3; in save_fsp_param()
3307 struct rv1126_sdram_params *sdram_params, in ddr_set_rate() argument
3314 u32 dramtype = sdram_params->base.dramtype; in ddr_set_rate()
3322 sdram_params_new->ch.cap_info.rank = sdram_params->ch.cap_info.rank; in ddr_set_rate()
3323 sdram_params_new->ch.cap_info.bw = sdram_params->ch.cap_info.bw; in ddr_set_rate()
3326 &sdram_params->ch.cap_info, dramtype, freq); in ddr_set_rate()
3497 struct rv1126_sdram_params *sdram_params) in ddr_set_rate_for_fsp() argument
3501 u32 dramtype = sdram_params->base.dramtype; in ddr_set_rate_for_fsp()
3525 if (get_wrlvl_val(dram, sdram_params)) in ddr_set_rate_for_fsp()
3532 ddr_set_rate(&dram_info, sdram_params, f1, in ddr_set_rate_for_fsp()
3533 sdram_params->base.ddr_freq, 1, 1, 1); in ddr_set_rate_for_fsp()
3537 ddr_set_rate(&dram_info, sdram_params, f2, f1, 2, 0, 1); in ddr_set_rate_for_fsp()
3541 ddr_set_rate(&dram_info, sdram_params, f3, f2, 3, 1, 1); in ddr_set_rate_for_fsp()
3547 ddr_set_rate(&dram_info, sdram_params, f0, f3, 0, 0, 1); in ddr_set_rate_for_fsp()
3549 ddr_set_rate(&dram_info, sdram_params, f0, sdram_params->base.ddr_freq, 1, 1, 1); in ddr_set_rate_for_fsp()
3568 struct rv1126_sdram_params *sdram_params; in sdram_init() local
3611 sdram_params = &sdram_configs[0]; in sdram_init()
3616 if (sdram_params->base.dramtype == DDR3 || in sdram_init()
3617 sdram_params->base.dramtype == DDR4) { in sdram_init()
3619 sdram_params->pctl_regs.pctl[0][1] |= 0x1 << 10; in sdram_init()
3621 sdram_params->pctl_regs.pctl[0][1] &= in sdram_init()
3624 ret = sdram_init_detect(&dram_info, sdram_params); in sdram_init()
3626 sdram_print_dram_type(sdram_params->base.dramtype); in sdram_init()
3628 printdec(sdram_params->base.ddr_freq); in sdram_init()
3632 print_ddr_info(sdram_params); in sdram_init()
3635 (u8)sdram_params->ch.cap_info.rank); in sdram_init()
3638 ddr_set_rate_for_fsp(&dram_info, sdram_params); in sdram_init()
3643 ddr_set_atags(&dram_info, sdram_params); in sdram_init()