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Searched refs:rk_setreg (Results 1 – 25 of 25) sorted by relevance

/OK3568_Linux_fs/u-boot/arch/arm/mach-rockchip/rk3368/
H A Drk3368.c259 rk_setreg(sgrf_soc_con_addr(5), SGRF_SOC_CON_SEC); in sgrf_init()
260 rk_setreg(sgrf_soc_con_addr(6), SGRF_SOC_CON_SEC); in sgrf_init()
261 rk_setreg(sgrf_soc_con_addr(7), SGRF_SOC_CON_SEC); in sgrf_init()
272 rk_setreg(sgrf_busdmac_addr(0), SGRF_BUSDMAC_CON0_SEC); in sgrf_init()
273 rk_setreg(sgrf_busdmac_addr(1), SGRF_BUSDMAC_CON1_SEC); in sgrf_init()
277 rk_setreg(&cru->softrst_con[1], DMA1_SRST_REQ); in sgrf_init()
278 rk_setreg(&cru->softrst_con[4], DMA2_SRST_REQ); in sgrf_init()
294 rk_setreg(GRF_SOC_CON15, 1 << 12); in arch_cpu_init()
300 rk_setreg(GRF_SOC_CON15, 1 << 13); in arch_cpu_init()
/OK3568_Linux_fs/u-boot/arch/arm/mach-rockchip/rk322x/
H A Drk322x.c32 rk_setreg(&grf->soc_con[2], 1 << 0); in arch_cpu_init()
35 rk_setreg(&grf->con_iomux, 0xf << 0); in arch_cpu_init()
38 rk_setreg(&grf->con_iomux, (1 << 11) | (1 << 8)); in arch_cpu_init()
/OK3568_Linux_fs/u-boot/arch/arm/mach-rockchip/rk3288/
H A Drk3288.c75 rk_setreg(&grf->soc_con2, 1 << 0); in arch_cpu_init()
78 rk_setreg(&grf->soc_con7, 1 << 15); in arch_cpu_init()
81 rk_setreg(CRU_CLKSEL_CON28, 1 << 15); in arch_cpu_init()
373 rk_setreg(GRF_SOC_CON2, 1 << 0); in board_early_init_f()
/OK3568_Linux_fs/u-boot/arch/arm/mach-rockchip/rk3328/
H A Drk3328.c59 rk_setreg(FW_DDR_CON_REG, 0x200); in arch_cpu_init()
62 rk_setreg(&grf->soc_con[4], 1 << 12); in arch_cpu_init()
/OK3568_Linux_fs/u-boot/drivers/crypto/rockchip/
H A Dcrypto_v1.c68 rk_setreg(&reg->crypto_ctrl, HASH_START); in rk_hash_direct_calc()
131 rk_setreg(&reg->crypto_ctrl, HASH_FLUSH); in rockchip_crypto_sha_init()
241 rk_setreg(&reg->crypto_ctrl, PKA_HASH_CTRL); in rockchip_crypto_rsa_verify()
257 rk_setreg(&reg->crypto_ctrl, PKA_START); in rockchip_crypto_rsa_verify()
/OK3568_Linux_fs/u-boot/drivers/video/rockchip/
H A Drk_lvds.c71 rk_setreg(&priv->grf->soc_con6, val); in rk_lvds_enable()
82 rk_setreg(&priv->grf->soc_con7, val); in rk_lvds_enable()
H A Drk3288_vop.c41 rk_setreg(&grf->io_vsel, 1 << 0); in rk3288_set_io_vsel()
H A Drk3288_hdmi.c32 rk_setreg(&grf->soc_con6, 1 << 15); in rk3288_hdmi_enable()
H A Drk_edp.c1061 rk_setreg(&priv->grf->soc_con12, 1 << 4); in rk_edp_probe()
1064 rk_setreg(&priv->grf->soc_con6, (vop_id == 1) ? (1 << 5) : (1 << 5)); in rk_edp_probe()
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dhardware.h19 #define rk_setreg(addr, set) writel((set) << 16 | (set), addr) macro
/OK3568_Linux_fs/u-boot/board/theobroma-systems/puma_rk3399/
H A Dpuma-rk3399.c183 rk_setreg(&grf->io_vsel, 1 << GRF_IO_VSEL_GPIO4CD_SHIFT); in setup_iodomain()
/OK3568_Linux_fs/u-boot/drivers/ram/rockchip/
H A Ddmc-rk3368.c144 rk_setreg(&grf->ddrc0_con0, NOC_RSP_ERR_STALL); in ddr_set_noc_spr_err_stall()
152 rk_setreg(&grf->ddrc0_con0, MSCH0_MAINDDR3_DDR3); in ddr_set_ddr3_mode()
345 rk_setreg(&cru->softrst_con[10], ctl_reset | phy_reset); in ddrctl_reset()
H A Dsdram_rk3288.c446 rk_setreg(&grf->soc_con0, 1 << (8 + channel)); in set_bandwidth_ratio()
/OK3568_Linux_fs/u-boot/drivers/clk/rockchip/
H A Dclk_rk3288.c248 rk_setreg(&pll->con3, 1 << PLL_RESET_SHIFT); in rkclk_set_pll()
1194 rk_setreg(&cru->cru_clksel_con[28], 1 << 15); in rk3288_clk_set_rate()
1197 rk_setreg(&cru->cru_clksel_con[6], 1 << 15); in rk3288_clk_set_rate()
1207 rk_setreg(&cru->cru_clkgate_con[7], 1 << 9); in rk3288_clk_set_rate()
H A Dclk_pll.c277 rk_setreg(base + pll->con_offset + 0x4, in rk3036_pll_set_rate()
440 rk_setreg(base + pll->con_offset + RK3588_PLLCON(1), in rk3588_pll_set_rate()
H A Dclk_rk3036.c80 rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); in rkclk_set_pll()
83 rk_setreg(&pll->con1, 1 << PLL_PD_SHIFT); in rkclk_set_pll()
H A Dclk_rk3328.c1012 rk_setreg(&grf->mac_con[1], BIT(10)); in rk3328_gmac2io_set_parent()
1049 rk_setreg(&grf->soc_con[4], BIT(14)); in rk3328_gmac2io_ext_set_parent()
1086 rk_setreg(&grf->mac_con[2], BIT(10)); in rk3328_gmac2phy_set_parent()
H A Dclk_rv1108.c89 rk_setreg(&pll->con3, 1 << DSMPD_SHIFT); in rkclk_set_pll()
91 rk_setreg(&pll->con3, 1 << GLOBAL_POWER_DOWN_SHIFT); in rkclk_set_pll()
H A Dclk_rk3066.c123 rk_setreg(&pll->con3, 1 << PLL_RESET_SHIFT); in rkclk_set_pll()
H A Dclk_rk3188.c121 rk_setreg(&pll->con3, 1 << PLL_RESET_SHIFT); in rkclk_set_pll()
H A Dclk_px30.c245 rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); in rkclk_set_pll()
247 rk_setreg(&pll->con1, 1 << PLL_PD_SHIFT); in rkclk_set_pll()
H A Dclk_rk3308.c1235 rk_setreg(&priv->cru->clksel_con[43], BIT(14)); in rk3308_mac_set_parent()
H A Dclk_rk3368.c1108 rk_setreg(&cru->clksel_con[43], GMAC_MUX_SEL_EXTCLK); in rk3368_gmac_set_parent()
H A Dclk_rk3399.c1321 rk_setreg(&priv->cru->clksel_con[19], BIT(4)); in rk3399_gmac_set_parent()
/OK3568_Linux_fs/u-boot/arch/arm/mach-rockchip/rk3036/
H A Dsdram_rk3036.c336 rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); in rkdclk_init()