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/OK3568_Linux_fs/kernel/drivers/misc/rk628/
H A Drk628_cru.c63 u32 postdiv1, fbdiv, dsmpd, postdiv2, refdiv, frac, bypass; in rk628_cru_clk_get_rate_pll() local
93 postdiv2 = (con1 & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT; in rk628_cru_clk_get_rate_pll()
112 do_div(foutpostdiv, postdiv2); in rk628_cru_clk_get_rate_pll()
123 u8 dsmpd = 1, postdiv1 = 0, postdiv2 = 0, refdiv = 0; in rk628_cru_clk_set_rate_pll() local
167 for (postdiv2 = 1; postdiv2 < 8; postdiv2++) { in rk628_cru_clk_set_rate_pll()
168 if (postdiv % postdiv2) in rk628_cru_clk_set_rate_pll()
171 postdiv1 = postdiv / postdiv2; in rk628_cru_clk_set_rate_pll()
177 if (postdiv2 > 7) in rk628_cru_clk_set_rate_pll()
180 fout *= postdiv1 * postdiv2; in rk628_cru_clk_set_rate_pll()
183 postdiv2 = 1; in rk628_cru_clk_set_rate_pll()
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/OK3568_Linux_fs/u-boot/drivers/clk/rockchip/
H A Dclk_pll.c84 u32 *postdiv2, in rockchip_pll_clk_set_postdiv() argument
91 for (*postdiv2 = 1; *postdiv2 <= 7; (*postdiv2)++) { in rockchip_pll_clk_set_postdiv()
92 freq = fout_hz * (*postdiv1) * (*postdiv2); in rockchip_pll_clk_set_postdiv()
104 *postdiv2 = 1; in rockchip_pll_clk_set_postdiv()
117 u32 f_frac, postdiv1, postdiv2; in rockchip_pll_clk_set_by_auto() local
123 rockchip_pll_clk_set_postdiv(fout_hz, &postdiv1, &postdiv2, &foutvco); in rockchip_pll_clk_set_by_auto()
125 rate_table->postdiv2 = postdiv2; in rockchip_pll_clk_set_by_auto()
142 rate_table->postdiv2); in rockchip_pll_clk_set_by_auto()
147 rate_table->postdiv1, rate_table->postdiv2, foutvco); in rockchip_pll_clk_set_by_auto()
264 __func__, rate->rate, rate->postdiv2, rate->dsmpd, rate->frac); in rk3036_pll_set_rate()
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H A Dclk_rk3399.c39 u32 postdiv2; member
51 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2, .freq = hz};
344 u32 refdiv, fbdiv, postdiv1, postdiv2; in rkclk_pll_get_rate() local
357 postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT; in rkclk_pll_get_rate()
359 return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; in rkclk_pll_get_rate()
370 u32 output_khz = vco_khz / div->postdiv1 / div->postdiv2; in rkclk_set_pll()
375 div->postdiv2, vco_khz, output_khz); in rkclk_set_pll()
396 (div->postdiv2 << PLL_POSTDIV2_SHIFT) | in rkclk_set_pll()
448 u32 postdiv1, postdiv2 = 1; in pll_para_config() local
463 postdiv2 = DIV_ROUND_UP(postdiv1, max_postdiv1); in pll_para_config()
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H A Dclk_rk3036.c52 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\
70 uint output_hz = vco_hz / div->postdiv1 / div->postdiv2; in rkclk_set_pll()
75 div->postdiv2, vco_hz, output_hz); in rkclk_set_pll()
89 (div->postdiv2 << PLL_POSTDIV2_SHIFT | in rkclk_set_pll()
204 uint32_t refdiv, fbdiv, postdiv1, postdiv2; in rkclk_pll_get_rate() local
233 postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT; in rkclk_pll_get_rate()
235 return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; in rkclk_pll_get_rate()
H A Dclk_rv1108.c34 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\
73 uint output_hz = vco_hz / div->postdiv1 / div->postdiv2; in rkclk_set_pll()
77 div->postdiv2, vco_hz, output_hz); in rkclk_set_pll()
96 div->postdiv2 << POSTDIV2_SHIFT | in rkclk_set_pll()
120 uint32_t refdiv, fbdiv, postdiv1, postdiv2; in rkclk_pll_get_rate() local
133 postdiv2 = (con1 & POSTDIV2_MASK) >> POSTDIV2_SHIFT; in rkclk_pll_get_rate()
135 freq = (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; in rkclk_pll_get_rate()
H A Dclk_px30.c39 .postdiv2 = _postdiv2, \
111 u32 postdiv1, postdiv2 = 1; in pll_clk_set_by_auto() local
126 postdiv2 = DIV_ROUND_UP(postdiv1, max_postdiv1); in pll_clk_set_by_auto()
127 postdiv1 = DIV_ROUND_UP(postdiv1, postdiv2); in pll_clk_set_by_auto()
130 vco_khz = rate_khz * postdiv1 * postdiv2; in pll_clk_set_by_auto()
133 postdiv2 > max_postdiv2) { in pll_clk_set_by_auto()
140 rate->postdiv2 = postdiv2; in pll_clk_set_by_auto()
229 output_hz = vco_hz / rate->postdiv1 / rate->postdiv2; in rkclk_set_pll()
233 rate->postdiv2, vco_hz, output_hz); in rkclk_set_pll()
253 (rate->postdiv2 << PLL_POSTDIV2_SHIFT | in rkclk_set_pll()
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/OK3568_Linux_fs/kernel/drivers/media/i2c/rk628/
H A Drk628_cru.c64 u32 postdiv1, fbdiv, dsmpd, postdiv2, refdiv, frac, bypass; in rk628_cru_clk_get_rate_pll() local
94 postdiv2 = (con1 & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT; in rk628_cru_clk_get_rate_pll()
113 do_div(foutpostdiv, postdiv2); in rk628_cru_clk_get_rate_pll()
124 u8 dsmpd = 1, postdiv1 = 0, postdiv2 = 0, refdiv = 0; in rk628_cru_clk_set_rate_pll() local
168 for (postdiv2 = 1; postdiv2 < 8; postdiv2++) { in rk628_cru_clk_set_rate_pll()
169 if (postdiv % postdiv2) in rk628_cru_clk_set_rate_pll()
172 postdiv1 = postdiv / postdiv2; in rk628_cru_clk_set_rate_pll()
177 if (postdiv2 > 7) in rk628_cru_clk_set_rate_pll()
186 fout *= postdiv1 * postdiv2; in rk628_cru_clk_set_rate_pll()
189 postdiv2 = 1; in rk628_cru_clk_set_rate_pll()
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/OK3568_Linux_fs/kernel/drivers/clk/rockchip/regmap/
H A Dclk-regmap-pll.c69 unsigned int postdiv1, fbdiv, dsmpd, postdiv2, refdiv, frac, bypass; in clk_regmap_pll_recalc_rate() local
81 postdiv2 = (con1 & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT; in clk_regmap_pll_recalc_rate()
100 do_div(foutpostdiv, postdiv2); in clk_regmap_pll_recalc_rate()
107 u8 *postdiv1, u8 *postdiv2, in clk_pll_round_rate() argument
220 if (postdiv2) in clk_pll_round_rate()
221 *postdiv2 = _postdiv2; in clk_pll_round_rate()
253 u8 refdiv, postdiv1, postdiv2, dsmpd, bypass; in clk_regmap_pll_set_rate() local
259 &postdiv2, &frac, &dsmpd, &bypass); in clk_regmap_pll_set_rate()
275 PLL_POSTDIV2(postdiv2) | PLL_REFDIV(refdiv)); in clk_regmap_pll_set_rate()
282 postdiv1, postdiv2); in clk_regmap_pll_set_rate()
/OK3568_Linux_fs/kernel/drivers/clk/pistachio/
H A Dclk-pll.c241 params->postdiv2 != old_postdiv2)) in pll_gf40lp_frac_set_rate()
244 if (params->postdiv2 > params->postdiv1) in pll_gf40lp_frac_set_rate()
254 (params->postdiv2 << PLL_FRAC_CTRL2_POSTDIV2_SHIFT); in pll_gf40lp_frac_set_rate()
273 u64 val, prediv, fbdiv, frac, postdiv1, postdiv2, rate; in pll_gf40lp_frac_recalc_rate() local
282 postdiv2 = (val >> PLL_FRAC_CTRL2_POSTDIV2_SHIFT) & in pll_gf40lp_frac_recalc_rate()
293 rate = do_div_round_closest(rate, (prediv * postdiv1 * postdiv2) << 24); in pll_gf40lp_frac_recalc_rate()
387 params->postdiv2 != old_postdiv2)) in pll_gf40lp_laint_set_rate()
390 if (params->postdiv2 > params->postdiv1) in pll_gf40lp_laint_set_rate()
400 (params->postdiv2 << PLL_INT_CTRL1_POSTDIV2_SHIFT); in pll_gf40lp_laint_set_rate()
413 u32 val, prediv, fbdiv, postdiv1, postdiv2; in pll_gf40lp_laint_recalc_rate() local
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H A Dclk.h100 unsigned long long postdiv2; member
/OK3568_Linux_fs/kernel/drivers/clk/rockchip/
H A Dclk-pll.c173 u32 *postdiv2, in rockchip_pll_clk_set_postdiv() argument
180 for (*postdiv2 = 1; *postdiv2 <= 7; (*postdiv2)++) { in rockchip_pll_clk_set_postdiv()
181 freq = fout_hz * (*postdiv1) * (*postdiv2); in rockchip_pll_clk_set_postdiv()
193 *postdiv2 = 1; in rockchip_pll_clk_set_postdiv()
207 u32 f_frac, postdiv1, postdiv2; in rockchip_pll_clk_set_by_auto() local
213 rockchip_pll_clk_set_postdiv(fout_hz, &postdiv1, &postdiv2, &foutvco); in rockchip_pll_clk_set_by_auto()
215 rate_table->postdiv2 = postdiv2; in rockchip_pll_clk_set_by_auto()
230 rate_table->postdiv2, rate_table->frac); in rockchip_pll_clk_set_by_auto()
237 rate_table->postdiv1, rate_table->postdiv2, foutvco); in rockchip_pll_clk_set_by_auto()
490 unsigned int fbdiv, postdiv1, refdiv, postdiv2; in rockchip_rk3036_pll_con_to_rate() local
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/OK3568_Linux_fs/u-boot/drivers/ram/rockchip/
H A Dsdram_rk3328.c79 unsigned int refdiv, postdiv1, postdiv2, fbdiv; in rkclk_set_dpll() local
86 postdiv2 = 2; in rkclk_set_dpll()
89 postdiv2 = 1; in rkclk_set_dpll()
92 postdiv2 = 1; in rkclk_set_dpll()
95 postdiv2 = 1; in rkclk_set_dpll()
98 postdiv2 = 1; in rkclk_set_dpll()
101 postdiv2 = 1; in rkclk_set_dpll()
103 fbdiv = (mhz * refdiv * postdiv1 * postdiv2) / 24; in rkclk_set_dpll()
107 writel(DSMPD(1) | POSTDIV2(postdiv2) | REFDIV(refdiv), in rkclk_set_dpll()
H A Dsdram_px30.c78 unsigned int refdiv, postdiv1, postdiv2, fbdiv; in rkclk_set_dpll() local
85 postdiv2 = 2; in rkclk_set_dpll()
88 postdiv2 = 1; in rkclk_set_dpll()
91 postdiv2 = 1; in rkclk_set_dpll()
94 postdiv2 = 1; in rkclk_set_dpll()
97 postdiv2 = 1; in rkclk_set_dpll()
100 postdiv2 = 1; in rkclk_set_dpll()
102 fbdiv = (mhz * refdiv * postdiv1 * postdiv2) / 24; in rkclk_set_dpll()
107 writel(DSMPD(1) | POSTDIV2(postdiv2) | REFDIV(refdiv), in rkclk_set_dpll()
H A Dsdram_rk3308.c93 pll_priv->postdiv2 << POSTDIV2_SHIFT | in pll_set()
135 rk3308_pll_div.postdiv2 = 1; in rkdclk_init()
145 rk3308_pll_div.postdiv2 = 1; in rkdclk_init()
153 rk3308_pll_div.postdiv2 = 1; in rkdclk_init()
189 rk3308_pll_div.postdiv2 = 1; in rkdclk_init()
197 rk3308_pll_div.postdiv2 = 1; in rkdclk_init()
266 rk3308_pll_div.postdiv2 = 1; in rkdclk_init()
329 rk3308_pll_div.postdiv2 = 1; in rkdclk_init()
H A Dsdram_rv1126.c317 unsigned int refdiv, postdiv1, postdiv2, fbdiv; in rkclk_set_dpll() local
332 postdiv2 = 4; in rkclk_set_dpll()
335 postdiv2 = 4; in rkclk_set_dpll()
338 postdiv2 = 2; in rkclk_set_dpll()
341 postdiv2 = 2; in rkclk_set_dpll()
344 postdiv2 = 1; in rkclk_set_dpll()
347 postdiv2 = 1; in rkclk_set_dpll()
349 fbdiv = (mhz * refdiv * postdiv1 * postdiv2) / 24; in rkclk_set_dpll()
368 writel(DSMPD(dsmpd) | POSTDIV2(postdiv2) | REFDIV(refdiv), in rkclk_set_dpll()
/OK3568_Linux_fs/kernel/arch/mips/ar7/
H A Dclock.c73 u32 postdiv2; member
262 int prediv, int postdiv, int postdiv2, int mul, u32 frequency) in tnetd7200_set_clock() argument
267 base, frequency, prediv, postdiv, postdiv2, mul); in tnetd7200_set_clock()
284 writel(DIVISOR_ENABLE_MASK | ((postdiv2 - 1) & 0x1F), &clock->postdiv2); in tnetd7200_set_clock()
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dclock.h74 .postdiv2 = _postdiv2, \
98 unsigned int postdiv2; member
H A Dcru_rk3036.h70 u32 postdiv2; member
H A Dcru_rv1108.h58 u32 postdiv2; member
H A Dcru_rv1106.h124 unsigned int postdiv2; member
H A Dcru_rk3528.h110 unsigned int postdiv2; member
H A Dcru_rv1126.h144 unsigned int postdiv2; member
H A Dcru_px30.h120 unsigned int postdiv2; member
/OK3568_Linux_fs/kernel/drivers/gpu/drm/msm/dsi/pll/
H A Ddsi_pll_28nm_8960.c54 u8 postdiv2; member
345 cached_state->postdiv2 = in dsi_pll_28nm_save_state()
371 cached_state->postdiv2); in dsi_pll_28nm_restore_state()
/OK3568_Linux_fs/kernel/drivers/clk/
H A Dclk-bm1880.c478 u32 postdiv1, postdiv2, denominator; in bm1880_pll_rate_calc() local
483 postdiv2 = (regval >> 12) & 0x7; in bm1880_pll_rate_calc()
486 denominator = refdiv * postdiv1 * postdiv2; in bm1880_pll_rate_calc()

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