63 	u32 postdiv1, fbdiv, dsmpd, postdiv2, refdiv, frac, bypass;  in rk628_cru_clk_get_rate_pll()  local
93 	postdiv2 = (con1 & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT;  in rk628_cru_clk_get_rate_pll()
112 	do_div(foutpostdiv, postdiv2);  in rk628_cru_clk_get_rate_pll()
123 	u8 dsmpd = 1, postdiv1 = 0, postdiv2 = 0, refdiv = 0;  in rk628_cru_clk_set_rate_pll()  local
167 		for (postdiv2 = 1; postdiv2 < 8; postdiv2++) {  in rk628_cru_clk_set_rate_pll()
168 			if (postdiv % postdiv2)  in rk628_cru_clk_set_rate_pll()
171 			postdiv1 = postdiv / postdiv2;  in rk628_cru_clk_set_rate_pll()
177 		if (postdiv2 > 7)  in rk628_cru_clk_set_rate_pll()
180 		fout *= postdiv1 * postdiv2;  in rk628_cru_clk_set_rate_pll()
183 		postdiv2 = 1;  in rk628_cru_clk_set_rate_pll()
237 	do_div(foutpostdiv, postdiv2);  in rk628_cru_clk_set_rate_pll()
243 			PLL_DSMPD(dsmpd) | PLL_POSTDIV2(postdiv2) |  in rk628_cru_clk_set_rate_pll()