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Searched refs:phy_base (Results 1 – 25 of 52) sorted by relevance

123

/OK3568_Linux_fs/u-boot/drivers/ram/rockchip/
H A Dsdram_phy_px30.c13 static void sdram_phy_dll_bypass_set(void __iomem *phy_base, u32 freq) in sdram_phy_dll_bypass_set() argument
19 setbits_le32(PHY_REG(phy_base, 0x13), 1 << 4); in sdram_phy_dll_bypass_set()
20 clrbits_le32(PHY_REG(phy_base, 0x14), 1 << 3); in sdram_phy_dll_bypass_set()
23 setbits_le32(PHY_REG(phy_base, j), 1 << 4); in sdram_phy_dll_bypass_set()
24 clrbits_le32(PHY_REG(phy_base, j + 0x1), 1 << 3); in sdram_phy_dll_bypass_set()
29 setbits_le32(PHY_REG(phy_base, 0xa4), 0x1f); in sdram_phy_dll_bypass_set()
31 clrbits_le32(PHY_REG(phy_base, 0xa4), 0x1f); in sdram_phy_dll_bypass_set()
46 writel(tmp, PHY_REG(phy_base, j)); in sdram_phy_dll_bypass_set()
50 static void sdram_phy_set_ds_odt(void __iomem *phy_base, in sdram_phy_set_ds_odt() argument
71 writel(cmd_drv, PHY_REG(phy_base, 0x11)); in sdram_phy_set_ds_odt()
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H A Dsdram_rv1126.c560 void __iomem *phy_base = dram->phy; in phy_pll_set() local
565 clrbits_le32(PHY_REG(phy_base, 0x53), PHY_PD_DISB); in phy_pll_set()
566 while (!(readl(PHY_REG(phy_base, 0x90)) & PHY_PLL_LOCK)) { in phy_pll_set()
590 writel(fbdiv & 0xff, PHY_REG(phy_base, 0x50)); in phy_pll_set()
591 clrsetbits_le32(PHY_REG(phy_base, 0x51), PHY_PBDIV_BIT9_MASK, in phy_pll_set()
593 clrsetbits_le32(PHY_REG(phy_base, 0x51), PHY_POSTDIV_EN_MASK, in phy_pll_set()
596 clrsetbits_le32(PHY_REG(phy_base, 0x52), in phy_pll_set()
598 clrsetbits_le32(PHY_REG(phy_base, 0x53), in phy_pll_set()
880 void __iomem *phy_base = dram->phy; in set_ds_odt() local
1037 clrsetbits_le32(PHY_REG(phy_base, 0x100), 0x1f, phy_ca_drv); in set_ds_odt()
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H A Dsdram_rk3328.c123 void __iomem *phy_base = dram->phy; in rkclk_configure_ddr() local
126 clrbits_le32(PHY_REG(phy_base, 0xef), 1 << 7); in rkclk_configure_ddr()
263 void __iomem *phy_base = dram->phy; in rx_deskew_switch_adjust() local
266 gate_val = MAX(readl(PHY_REG(phy_base, 0xfb + i)), gate_val); in rx_deskew_switch_adjust()
270 clrsetbits_le32(PHY_REG(phy_base, 0x6e), 0xc, (deskew_val & 0x3) << 2); in rx_deskew_switch_adjust()
271 clrsetbits_le32(PHY_REG(phy_base, 0x6f), 0x7 << 4, in rx_deskew_switch_adjust()
277 void __iomem *phy_base = dram->phy; in tx_deskew_switch_adjust() local
279 clrsetbits_le32(PHY_REG(phy_base, 0x6e), 0x3, 1); in tx_deskew_switch_adjust()
/OK3568_Linux_fs/u-boot/arch/arm/mach-uniphier/dram/
H A Dumc-pxs2.c58 static void ddrphy_fifo_reset(void __iomem *phy_base) in ddrphy_fifo_reset() argument
62 tmp = readl(phy_base + MPHY_PGCR0); in ddrphy_fifo_reset()
64 writel(tmp, phy_base + MPHY_PGCR0); in ddrphy_fifo_reset()
69 writel(tmp, phy_base + MPHY_PGCR0); in ddrphy_fifo_reset()
74 static void ddrphy_vt_ctrl(void __iomem *phy_base, int enable) in ddrphy_vt_ctrl() argument
78 tmp = readl(phy_base + MPHY_PGCR1); in ddrphy_vt_ctrl()
85 writel(tmp, phy_base + MPHY_PGCR1); in ddrphy_vt_ctrl()
88 while (!(readl(phy_base + MPHY_PGSR1) & MPHY_PGSR1_VTSTOP)) in ddrphy_vt_ctrl()
93 static void ddrphy_dqs_delay_fixup(void __iomem *phy_base, int nr_dx, int step) in ddrphy_dqs_delay_fixup() argument
97 void __iomem *dx_base = phy_base + MPHY_DX_BASE; in ddrphy_dqs_delay_fixup()
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H A Dddrphy-ld4.c31 int uniphier_ld4_ddrphy_init(void __iomem *phy_base, int freq, bool ddr3plus) in uniphier_ld4_ddrphy_init() argument
48 writel(0x0300c473, phy_base + PHY_PGCR1); in uniphier_ld4_ddrphy_init()
49 writel(ddrphy_ptr0[freq_e], phy_base + PHY_PTR0); in uniphier_ld4_ddrphy_init()
50 writel(ddrphy_ptr1[freq_e], phy_base + PHY_PTR1); in uniphier_ld4_ddrphy_init()
51 writel(0x00083DEF, phy_base + PHY_PTR2); in uniphier_ld4_ddrphy_init()
52 writel(ddrphy_ptr3[freq_e], phy_base + PHY_PTR3); in uniphier_ld4_ddrphy_init()
53 writel(ddrphy_ptr4[freq_e], phy_base + PHY_PTR4); in uniphier_ld4_ddrphy_init()
54 writel(0xF004001A, phy_base + PHY_DSGCR); in uniphier_ld4_ddrphy_init()
57 tmp = readl(phy_base + PHY_DXCCR); in uniphier_ld4_ddrphy_init()
60 writel(tmp, phy_base + PHY_DXCCR); in uniphier_ld4_ddrphy_init()
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H A Dcmd_ddrmphy.c72 void __iomem *phy_base, *dx_base; in dump_loop() local
76 phy_base = ioremap(param->phy[phy].base, SZ_4K); in dump_loop()
77 dx_base = phy_base + MPHY_DX_BASE; in dump_loop()
86 iounmap(phy_base); in dump_loop()
92 void __iomem *phy_base, *zq_base; in zq_dump() local
100 phy_base = ioremap(param->phy[phy].base, SZ_4K); in zq_dump()
101 zq_base = phy_base + MPHY_ZQ_BASE; in zq_dump()
122 iounmap(phy_base); in zq_dump()
228 { int ofst = MPHY_ ## x; void __iomem *reg = phy_base + ofst; \
235 void __iomem *reg = phy_base + ofst; \
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H A Dddrphy-training.c18 void ddrphy_prepare_training(void __iomem *phy_base, int rank) in ddrphy_prepare_training() argument
20 void __iomem *dx_base = phy_base + PHY_DX_BASE; in ddrphy_prepare_training()
34 tmp = readl(phy_base + PHY_DTCR); in ddrphy_prepare_training()
43 writel(tmp, phy_base + PHY_DTCR); in ddrphy_prepare_training()
104 int ddrphy_training(void __iomem *phy_base) in ddrphy_training() argument
120 writel(init_flag, phy_base + PHY_PIR); in ddrphy_training()
129 pgsr0 = readl(phy_base + PHY_PGSR0); in ddrphy_training()
H A Dcmd_ddrphy.c87 void __iomem *phy_base, *dx_base; in dump_loop() local
91 phy_base = ioremap(param->phy[phy].base, SZ_4K); in dump_loop()
92 dx_base = phy_base + PHY_DX_BASE; in dump_loop()
101 iounmap(phy_base); in dump_loop()
202 { int ofst = PHY_ ## x; void __iomem *reg = phy_base + ofst; \
210 void __iomem *reg = phy_base + ofst; \
217 void __iomem *phy_base; in reg_dump() local
223 phy_base = ioremap(param->phy[phy].base, SZ_4K); in reg_dump()
226 phy, ptr_to_uint(phy_base)); in reg_dump()
259 iounmap(phy_base); in reg_dump()
H A Dddrphy-init.h13 int uniphier_ld4_ddrphy_init(void __iomem *phy_base, int freq, bool ddr3plus);
14 void ddrphy_prepare_training(void __iomem *phy_base, int rank);
15 int ddrphy_training(void __iomem *phy_base);
H A Dumc-pro4.c135 void __iomem *phy_base = dc_base + 0x00001000; in umc_ch_init() local
147 ret = uniphier_ld4_ddrphy_init(phy_base, freq, ddr3plus); in umc_ch_init()
151 ddrphy_prepare_training(phy_base, phy); in umc_ch_init()
152 ret = ddrphy_training(phy_base); in umc_ch_init()
156 phy_base += 0x00001000; in umc_ch_init()
H A Dumc-ld4.c148 void __iomem *phy_base = dc_base + 0x00001000; in umc_ch_init() local
157 ret = uniphier_ld4_ddrphy_init(phy_base, freq, ddr3plus); in umc_ch_init()
161 ddrphy_prepare_training(phy_base, umc_get_rank(ch)); in umc_ch_init()
162 ret = ddrphy_training(phy_base); in umc_ch_init()
H A Dumc-sld8.c151 void __iomem *phy_base = dc_base + 0x00001000; in umc_ch_init() local
160 ret = uniphier_ld4_ddrphy_init(phy_base, freq, ddr3plus); in umc_ch_init()
164 ddrphy_prepare_training(phy_base, umc_get_rank(ch)); in umc_ch_init()
165 ret = ddrphy_training(phy_base); in umc_ch_init()
/OK3568_Linux_fs/kernel/drivers/phy/samsung/
H A Dphy-exynos-pcie.c69 void __iomem *phy_base; member
89 exynos_pcie_phy_writel(ep->phy_base, 0x29, PCIE_PHY_DCC_FEEDBACK); in exynos5440_pcie_phy_init()
92 exynos_pcie_phy_writel(ep->phy_base, 0xd5, PCIE_PHY_IMPEDANCE); in exynos5440_pcie_phy_init()
95 exynos_pcie_phy_writel(ep->phy_base, 0x14, PCIE_PHY_PLL_DIV_0); in exynos5440_pcie_phy_init()
96 exynos_pcie_phy_writel(ep->phy_base, 0x12, PCIE_PHY_PLL_DIV_1); in exynos5440_pcie_phy_init()
99 exynos_pcie_phy_writel(ep->phy_base, 0x7f, PCIE_PHY_TRSV0_DRV_LVL); in exynos5440_pcie_phy_init()
102 exynos_pcie_phy_writel(ep->phy_base, 0x0, PCIE_PHY_TRSV0_EMP_LVL); in exynos5440_pcie_phy_init()
105 exynos_pcie_phy_writel(ep->phy_base, 0xe7, PCIE_PHY_PLL_BIAS); in exynos5440_pcie_phy_init()
106 exynos_pcie_phy_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV0_RXCDR); in exynos5440_pcie_phy_init()
107 exynos_pcie_phy_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV1_RXCDR); in exynos5440_pcie_phy_init()
[all …]
/OK3568_Linux_fs/u-boot/drivers/phy/
H A Dphy-rockchip-inno-usb2.c161 void __iomem *phy_base; member
578 rphy->phy_base = (void __iomem *)dev_read_addr(dev); in rockchip_usb2phy_probe()
579 if (IS_ERR(rphy->phy_base)) { in rockchip_usb2phy_probe()
818 reg = readl(rphy->phy_base + 0x70); in rv1106_usb2phy_tuning()
819 writel(reg | BIT(2), rphy->phy_base + 0x70); in rv1106_usb2phy_tuning()
829 if (IS_ERR(rphy->phy_base)) { in rk3528_usb2phy_tuning()
830 return PTR_ERR(rphy->phy_base); in rk3528_usb2phy_tuning()
834 reg = readl(rphy->phy_base + 0x30); in rk3528_usb2phy_tuning()
835 writel(reg & ~BIT(2), rphy->phy_base + 0x30); in rk3528_usb2phy_tuning()
838 reg = readl(rphy->phy_base + 0x0430); in rk3528_usb2phy_tuning()
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/OK3568_Linux_fs/kernel/drivers/phy/marvell/
H A Dphy-berlin-sata.c62 u32 phy_base; member
66 u32 phy_base, u32 reg, u32 mask, u32 val) in phy_berlin_sata_reg_setbits() argument
71 writel(phy_base + reg, ctrl_reg + PORT_VSR_ADDR); in phy_berlin_sata_reg_setbits()
104 phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x01, in phy_berlin_sata_power_on()
109 phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x25, in phy_berlin_sata_power_on()
113 phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x23, in phy_berlin_sata_power_on()
117 phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x02, in phy_berlin_sata_power_on()
224 priv->phy_base = BG2_PHY_BASE; in phy_berlin_sata_probe()
226 priv->phy_base = BG2Q_PHY_BASE; in phy_berlin_sata_probe()
/OK3568_Linux_fs/kernel/drivers/clk/ux500/
H A Dclk-prcc.c95 resource_size_t phy_base, in clk_reg_prcc() argument
113 clk->base = ioremap(phy_base, SZ_4K); in clk_reg_prcc()
143 resource_size_t phy_base, in clk_reg_prcc_pclk() argument
147 return clk_reg_prcc(name, parent_name, phy_base, cg_sel, flags, in clk_reg_prcc_pclk()
153 resource_size_t phy_base, in clk_reg_prcc_kclk() argument
157 return clk_reg_prcc(name, parent_name, phy_base, cg_sel, flags, in clk_reg_prcc_kclk()
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dsdram_phy_px30.h55 void phy_soft_reset(void __iomem *phy_base);
56 void phy_dram_set_bw(void __iomem *phy_base, u32 bw);
57 void phy_cfg(void __iomem *phy_base,
60 int phy_data_training(void __iomem *phy_base, u32 cs, u32 dramtype);
/OK3568_Linux_fs/kernel/drivers/phy/ti/
H A Dphy-omap-usb2.c57 void __iomem *phy_base; member
240 val = omap_usb_readl(phy->phy_base, USB2PHY_ANA_CONFIG1); in omap_usb_init()
242 omap_usb_writel(phy->phy_base, USB2PHY_ANA_CONFIG1, val); in omap_usb_init()
246 val = omap_usb_readl(phy->phy_base, USB2PHY_CHRG_DET); in omap_usb_init()
249 omap_usb_writel(phy->phy_base, USB2PHY_CHRG_DET, val); in omap_usb_init()
407 phy->phy_base = devm_ioremap_resource(&pdev->dev, res); in omap_usb2_probe()
408 if (IS_ERR(phy->phy_base)) in omap_usb2_probe()
409 return PTR_ERR(phy->phy_base); in omap_usb2_probe()
/OK3568_Linux_fs/kernel/drivers/phy/rockchip/
H A Dphy-rockchip-usb.c1048 struct rockchip_usb_phy_base *phy_base; in rockchip_usb_phy_probe() local
1054 phy_base = devm_kzalloc(dev, sizeof(*phy_base), GFP_KERNEL); in rockchip_usb_phy_probe()
1055 if (!phy_base) in rockchip_usb_phy_probe()
1064 phy_base->pdata = match->data; in rockchip_usb_phy_probe()
1066 phy_base->dev = dev; in rockchip_usb_phy_probe()
1067 phy_base->reg_base = ERR_PTR(-ENODEV); in rockchip_usb_phy_probe()
1069 phy_base->reg_base = syscon_node_to_regmap( in rockchip_usb_phy_probe()
1071 if (IS_ERR(phy_base->reg_base)) in rockchip_usb_phy_probe()
1072 phy_base->reg_base = syscon_regmap_lookup_by_phandle( in rockchip_usb_phy_probe()
1074 if (IS_ERR(phy_base->reg_base)) { in rockchip_usb_phy_probe()
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H A Dphy-rockchip-inno-usb2.c337 void __iomem *phy_base; member
466 if (!phy_property_enabled(rphy->phy_base, &rphy->phy_cfg->clkout_ctl_phy)) { in rockchip_usb2phy_clk480m_prepare()
467 phy_property_enable(rphy->phy_base, &rphy->phy_cfg->clkout_ctl_phy, true); in rockchip_usb2phy_clk480m_prepare()
492 phy_property_enable(rphy->phy_base, &rphy->phy_cfg->clkout_ctl_phy, false); in rockchip_usb2phy_clk480m_unprepare()
504 return phy_property_enabled(rphy->phy_base, &rphy->phy_cfg->clkout_ctl_phy); in rockchip_usb2phy_clk480m_prepared()
2282 rphy->phy_base = devm_ioremap_resource(dev, res); in rockchip_usb2phy_probe()
2283 if (IS_ERR(rphy->phy_base)) in rockchip_usb2phy_probe()
2284 return PTR_ERR(rphy->phy_base); in rockchip_usb2phy_probe()
2737 phy_clear_bits(rphy->phy_base + 0x30, BIT(2)); in rk3528_usb2phy_tuning()
2740 phy_clear_bits(rphy->phy_base + 0x430, BIT(2)); in rk3528_usb2phy_tuning()
[all …]
/OK3568_Linux_fs/u-boot/drivers/usb/host/
H A Dxhci-exynos5.c38 fdt_addr_t phy_base; member
81 plat->phy_base = fdtdec_get_addr(blob, node, "reg"); in xhci_usb_ofdata_to_platdata()
82 if (plat->phy_base == FDT_ADDR_T_NONE) { in xhci_usb_ofdata_to_platdata()
213 ctx->usb3_phy = (struct exynos_usb3_phy *)plat->phy_base; in xhci_usb_probe()
H A Dehci-exynos.c31 fdt_addr_t phy_base; member
72 plat->phy_base = fdtdec_get_addr(blob, node, "reg"); in ehci_usb_ofdata_to_platdata()
73 if (plat->phy_base == FDT_ADDR_T_NONE) { in ehci_usb_ofdata_to_platdata()
221 ctx->usb = (struct exynos_usb_phy *)plat->phy_base; in ehci_usb_probe()
/OK3568_Linux_fs/kernel/drivers/pci/controller/dwc/
H A Dpcie-artpec6.c35 void __iomem *phy_base; /* DT phy */ member
162 val = readl(artpec6_pcie->phy_base + PHY_STATUS); in artpec6_pcie_wait_for_phy_a6()
190 phy_status_tx = readw(artpec6_pcie->phy_base + PHY_TX_ASIC_OUT); in artpec6_pcie_wait_for_phy_a7()
191 phy_status_rx = readw(artpec6_pcie->phy_base + PHY_RX_ASIC_OUT); in artpec6_pcie_wait_for_phy_a7()
476 artpec6_pcie->phy_base = in artpec6_pcie_probe()
478 if (IS_ERR(artpec6_pcie->phy_base)) in artpec6_pcie_probe()
479 return PTR_ERR(artpec6_pcie->phy_base); in artpec6_pcie_probe()
H A Dpcie-kirin.c84 void __iomem *phy_base; member
111 writel(val, kirin_pcie->phy_base + reg); in kirin_apb_phy_writel()
116 return readl(kirin_pcie->phy_base + reg); in kirin_apb_phy_readl()
155 kirin_pcie->phy_base = in kirin_pcie_get_resource()
157 if (IS_ERR(kirin_pcie->phy_base)) in kirin_pcie_get_resource()
158 return PTR_ERR(kirin_pcie->phy_base); in kirin_pcie_get_resource()
/OK3568_Linux_fs/kernel/drivers/ata/
H A Dsata_highbank.c57 void __iomem *phy_base; member
219 writel(CPHY_MAP(dev, addr), port_data[sata_port].phy_base + 0x800); in __combo_phy_reg_read()
220 data = readl(port_data[sata_port].phy_base + CPHY_ADDR(addr)); in __combo_phy_reg_read()
229 writel(CPHY_MAP(dev, addr), port_data[sata_port].phy_base + 0x800); in __combo_phy_reg_write()
230 writel(data, port_data[sata_port].phy_base + CPHY_ADDR(addr)); in __combo_phy_reg_write()
261 if (unlikely(port_data[sata_port].phy_base == NULL)) in highbank_cphy_disable_overrides()
316 if (unlikely(port_data[sata_port].phy_base == NULL)) in highbank_cphy_override_lane()
358 port_data[port].phy_base = cphy_base[phy]; in highbank_initialize_phys()

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