1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2014 Panasonic Corporation
3*4882a593Smuzhiyun * Copyright (C) 2015-2016 Socionext Inc.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <common.h>
9*4882a593Smuzhiyun #include <linux/errno.h>
10*4882a593Smuzhiyun #include <linux/io.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include "ddrphy-init.h"
13*4882a593Smuzhiyun #include "ddrphy-regs.h"
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun enum dram_freq {
16*4882a593Smuzhiyun DRAM_FREQ_1333M,
17*4882a593Smuzhiyun DRAM_FREQ_1600M,
18*4882a593Smuzhiyun DRAM_FREQ_NR,
19*4882a593Smuzhiyun };
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun static u32 ddrphy_ptr0[DRAM_FREQ_NR] = {0x0a806844, 0x0c807d04};
22*4882a593Smuzhiyun static u32 ddrphy_ptr1[DRAM_FREQ_NR] = {0x208e0124, 0x2710015E};
23*4882a593Smuzhiyun static u32 ddrphy_ptr3[DRAM_FREQ_NR] = {0x0f051616, 0x12061A80};
24*4882a593Smuzhiyun static u32 ddrphy_ptr4[DRAM_FREQ_NR] = {0x06ae08d6, 0x08027100};
25*4882a593Smuzhiyun static u32 ddrphy_dtpr0[DRAM_FREQ_NR] = {0x85589955, 0x999cbb66};
26*4882a593Smuzhiyun static u32 ddrphy_dtpr1[DRAM_FREQ_NR] = {0x1a8363c0, 0x1a878400};
27*4882a593Smuzhiyun static u32 ddrphy_dtpr2[DRAM_FREQ_NR] = {0x5002c200, 0xa00214f8};
28*4882a593Smuzhiyun static u32 ddrphy_mr0[DRAM_FREQ_NR] = {0x00000b51, 0x00000d71};
29*4882a593Smuzhiyun static u32 ddrphy_mr2[DRAM_FREQ_NR] = {0x00000290, 0x00000298};
30*4882a593Smuzhiyun
uniphier_ld4_ddrphy_init(void __iomem * phy_base,int freq,bool ddr3plus)31*4882a593Smuzhiyun int uniphier_ld4_ddrphy_init(void __iomem *phy_base, int freq, bool ddr3plus)
32*4882a593Smuzhiyun {
33*4882a593Smuzhiyun enum dram_freq freq_e;
34*4882a593Smuzhiyun u32 tmp;
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun switch (freq) {
37*4882a593Smuzhiyun case 1333:
38*4882a593Smuzhiyun freq_e = DRAM_FREQ_1333M;
39*4882a593Smuzhiyun break;
40*4882a593Smuzhiyun case 1600:
41*4882a593Smuzhiyun freq_e = DRAM_FREQ_1600M;
42*4882a593Smuzhiyun break;
43*4882a593Smuzhiyun default:
44*4882a593Smuzhiyun printf("unsupported DRAM frequency %d MHz\n", freq);
45*4882a593Smuzhiyun return -EINVAL;
46*4882a593Smuzhiyun }
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun writel(0x0300c473, phy_base + PHY_PGCR1);
49*4882a593Smuzhiyun writel(ddrphy_ptr0[freq_e], phy_base + PHY_PTR0);
50*4882a593Smuzhiyun writel(ddrphy_ptr1[freq_e], phy_base + PHY_PTR1);
51*4882a593Smuzhiyun writel(0x00083DEF, phy_base + PHY_PTR2);
52*4882a593Smuzhiyun writel(ddrphy_ptr3[freq_e], phy_base + PHY_PTR3);
53*4882a593Smuzhiyun writel(ddrphy_ptr4[freq_e], phy_base + PHY_PTR4);
54*4882a593Smuzhiyun writel(0xF004001A, phy_base + PHY_DSGCR);
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun /* change the value of the on-die pull-up/pull-down registors */
57*4882a593Smuzhiyun tmp = readl(phy_base + PHY_DXCCR);
58*4882a593Smuzhiyun tmp &= ~0x0ee0;
59*4882a593Smuzhiyun tmp |= PHY_DXCCR_DQSNRES_688_OHM | PHY_DXCCR_DQSRES_688_OHM;
60*4882a593Smuzhiyun writel(tmp, phy_base + PHY_DXCCR);
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun writel(0x0000040B, phy_base + PHY_DCR);
63*4882a593Smuzhiyun writel(ddrphy_dtpr0[freq_e], phy_base + PHY_DTPR0);
64*4882a593Smuzhiyun writel(ddrphy_dtpr1[freq_e], phy_base + PHY_DTPR1);
65*4882a593Smuzhiyun writel(ddrphy_dtpr2[freq_e], phy_base + PHY_DTPR2);
66*4882a593Smuzhiyun writel(ddrphy_mr0[freq_e], phy_base + PHY_MR0);
67*4882a593Smuzhiyun writel(0x00000006, phy_base + PHY_MR1);
68*4882a593Smuzhiyun writel(ddrphy_mr2[freq_e], phy_base + PHY_MR2);
69*4882a593Smuzhiyun writel(ddr3plus ? 0x00000800 : 0x00000000, phy_base + PHY_MR3);
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun while (!(readl(phy_base + PHY_PGSR0) & PHY_PGSR0_IDONE))
72*4882a593Smuzhiyun ;
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun writel(0x0300C473, phy_base + PHY_PGCR1);
75*4882a593Smuzhiyun writel(0x0000005D, phy_base + PHY_ZQ_BASE + PHY_ZQ_CR1);
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun return 0;
78*4882a593Smuzhiyun }
79