1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2018 Rockchip Electronics Co., Ltd 4 */ 5 6 #ifndef _ASM_ARCH_SDRAM_PHY_PX30_H 7 #define _ASM_ARCH_SDRAM_PHY_PX30_H 8 #include <asm/arch/sdram_common.h> 9 #include <asm/arch/sdram_phy_ron_rtt_px30.h> 10 11 struct ddr_phy_regs { 12 u32 phy[5][2]; 13 }; 14 15 #define PHY_REG(base, n) ((base) + 4 * (n)) 16 17 /* PHY_REG0 */ 18 #define DIGITAL_DERESET BIT(3) 19 #define ANALOG_DERESET BIT(2) 20 #define DIGITAL_RESET (0 << 3) 21 #define ANALOG_RESET (0 << 2) 22 23 /* PHY_REG1 */ 24 #define PHY_DDR2 (0) 25 #define PHY_LPDDR2 (1) 26 #define PHY_DDR3 (2) 27 #define PHY_LPDDR3 (3) 28 #define PHY_DDR4 (4) 29 #define PHY_BL_4 (0 << 2) 30 #define PHY_BL_8 BIT(2) 31 32 /* PHY_REG2 */ 33 #define PHY_DTT_EN BIT(0) 34 #define PHY_DTT_DISB (0 << 0) 35 #define PHY_WRITE_LEVELING_EN BIT(2) 36 #define PHY_WRITE_LEVELING_DISB (0 << 2) 37 #define PHY_SELECT_CS0 (2) 38 #define PHY_SELECT_CS1 (1) 39 #define PHY_SELECT_CS0_1 (0) 40 #define PHY_WRITE_LEVELING_SELECTCS(n) ((n) << 6) 41 #define PHY_DATA_TRAINING_SELECTCS(n) ((n) << 4) 42 43 struct ddr_phy_skew { 44 u32 a0_a1_skew[15]; 45 u32 cs0_dm0_skew[11]; 46 u32 cs0_dm1_skew[11]; 47 u32 cs0_dm2_skew[11]; 48 u32 cs0_dm3_skew[11]; 49 u32 cs1_dm0_skew[11]; 50 u32 cs1_dm1_skew[11]; 51 u32 cs1_dm2_skew[11]; 52 u32 cs1_dm3_skew[11]; 53 }; 54 55 void phy_soft_reset(void __iomem *phy_base); 56 void phy_dram_set_bw(void __iomem *phy_base, u32 bw); 57 void phy_cfg(void __iomem *phy_base, 58 struct ddr_phy_regs *phy_regs, struct ddr_phy_skew *skew, 59 struct sdram_base_params *base, u32 bw); 60 int phy_data_training(void __iomem *phy_base, u32 cs, u32 dramtype); 61 62 #endif 63