58 static void ddrphy_fifo_reset(void __iomem *phy_base)  in ddrphy_fifo_reset()  argument
62 	tmp = readl(phy_base + MPHY_PGCR0);  in ddrphy_fifo_reset()
64 	writel(tmp, phy_base + MPHY_PGCR0);  in ddrphy_fifo_reset()
69 	writel(tmp, phy_base + MPHY_PGCR0);  in ddrphy_fifo_reset()
74 static void ddrphy_vt_ctrl(void __iomem *phy_base, int enable)  in ddrphy_vt_ctrl()  argument
78 	tmp = readl(phy_base + MPHY_PGCR1);  in ddrphy_vt_ctrl()
85 	writel(tmp, phy_base + MPHY_PGCR1);  in ddrphy_vt_ctrl()
88 		while (!(readl(phy_base + MPHY_PGSR1) & MPHY_PGSR1_VTSTOP))  in ddrphy_vt_ctrl()
93 static void ddrphy_dqs_delay_fixup(void __iomem *phy_base, int nr_dx, int step)  in ddrphy_dqs_delay_fixup()  argument
97 	void __iomem *dx_base = phy_base + MPHY_DX_BASE;  in ddrphy_dqs_delay_fixup()
99 	ddrphy_vt_ctrl(phy_base, 0);  in ddrphy_dqs_delay_fixup()
111 	ddrphy_vt_ctrl(phy_base, 1);  in ddrphy_dqs_delay_fixup()
114 static int ddrphy_get_system_latency(void __iomem *phy_base, int width)  in ddrphy_get_system_latency()  argument
116 	void __iomem *dx_base = phy_base + MPHY_DX_BASE;  in ddrphy_get_system_latency()
142 static void ddrphy_init(void __iomem *phy_base, enum dram_freq freq, int width,  in ddrphy_init()  argument
152 	writel(MPHY_PIR_ZCALBYP,        phy_base + MPHY_PIR);  in ddrphy_init()
157 	writel(0x07d81e37, phy_base + MPHY_PGCR0);  in ddrphy_init()
158 	writel(0x0200c4e0, phy_base + MPHY_PGCR1);  in ddrphy_init()
163 	writel(tmp, phy_base + MPHY_PGCR2);  in ddrphy_init()
165 	writel(ddrphy_ptr0[freq], phy_base + MPHY_PTR0);  in ddrphy_init()
166 	writel(ddrphy_ptr1[freq], phy_base + MPHY_PTR1);  in ddrphy_init()
167 	writel(0x00083def, phy_base + MPHY_PTR2);  in ddrphy_init()
168 	writel(ddrphy_ptr3[freq], phy_base + MPHY_PTR3);  in ddrphy_init()
169 	writel(ddrphy_ptr4[freq], phy_base + MPHY_PTR4);  in ddrphy_init()
171 	writel(ddrphy_acbdlr0[ch], phy_base + MPHY_ACBDLR0);  in ddrphy_init()
173 	writel(0x55555555, phy_base + MPHY_ACIOCR1);  in ddrphy_init()
174 	writel(0x00000000, phy_base + MPHY_ACIOCR2);  in ddrphy_init()
175 	writel(0x55555555, phy_base + MPHY_ACIOCR3);  in ddrphy_init()
176 	writel(0x00000000, phy_base + MPHY_ACIOCR4);  in ddrphy_init()
177 	writel(0x00000055, phy_base + MPHY_ACIOCR5);  in ddrphy_init()
178 	writel(0x00181aa4, phy_base + MPHY_DXCCR);  in ddrphy_init()
180 	writel(0x0024641e, phy_base + MPHY_DSGCR);  in ddrphy_init()
181 	writel(0x0000040b, phy_base + MPHY_DCR);  in ddrphy_init()
182 	writel(ddrphy_dtpr0[freq], phy_base + MPHY_DTPR0);  in ddrphy_init()
183 	writel(ddrphy_dtpr1[freq], phy_base + MPHY_DTPR1);  in ddrphy_init()
184 	writel(ddrphy_dtpr2[freq], phy_base + MPHY_DTPR2);  in ddrphy_init()
185 	writel(ddrphy_dtpr3[freq], phy_base + MPHY_DTPR3);  in ddrphy_init()
186 	writel(ddrphy_mr0[freq], phy_base + MPHY_MR0);  in ddrphy_init()
187 	writel(0x00000006, phy_base + MPHY_MR1);  in ddrphy_init()
188 	writel(ddrphy_mr2[freq], phy_base + MPHY_MR2);  in ddrphy_init()
189 	writel(0x00000000, phy_base + MPHY_MR3);  in ddrphy_init()
194 	writel(0x90003087 | tmp, phy_base + MPHY_DTCR);  in ddrphy_init()
196 	writel(0x00000000, phy_base + MPHY_DTAR0);  in ddrphy_init()
197 	writel(0x00000008, phy_base + MPHY_DTAR1);  in ddrphy_init()
198 	writel(0x00000010, phy_base + MPHY_DTAR2);  in ddrphy_init()
199 	writel(0x00000018, phy_base + MPHY_DTAR3);  in ddrphy_init()
200 	writel(0xdd22ee11, phy_base + MPHY_DTDR0);  in ddrphy_init()
201 	writel(0x7788bb44, phy_base + MPHY_DTDR1);  in ddrphy_init()
204 	writel(0x04048900, phy_base + MPHY_ZQCR);  in ddrphy_init()
206 	zq_base = phy_base + MPHY_ZQ_BASE;  in ddrphy_init()
217 	dx_base = phy_base + MPHY_DX_BASE;  in ddrphy_init()
231 	while (!(readl(phy_base + MPHY_PGSR0) & MPHY_PGSR0_IDONE))  in ddrphy_init()
234 	ddrphy_dqs_delay_fixup(phy_base, nr_dx, -4);  in ddrphy_init()
310 static int __ddrphy_training(void __iomem *phy_base,  in __ddrphy_training()  argument
327 	writel(init_flag, phy_base + MPHY_PIR);  in __ddrphy_training()
336 		pgsr0 = readl(phy_base + MPHY_PGSR0);  in __ddrphy_training()
354 static int ddrphy_impedance_calibration(void __iomem *phy_base)  in ddrphy_impedance_calibration()  argument
359 	ret = __ddrphy_training(phy_base, impedance_calibration_sequence);  in ddrphy_impedance_calibration()
371 	tmp = readl(phy_base + MPHY_ZQCR);  in ddrphy_impedance_calibration()
373 	writel(tmp, phy_base + MPHY_ZQCR);  in ddrphy_impedance_calibration()
376 	writel(tmp, phy_base + MPHY_ZQCR);  in ddrphy_impedance_calibration()
381 static int ddrphy_dram_init(void __iomem *phy_base)  in ddrphy_dram_init()  argument
383 	return __ddrphy_training(phy_base, dram_init_sequence);  in ddrphy_dram_init()
386 static int ddrphy_training(void __iomem *phy_base)  in ddrphy_training()  argument
388 	return __ddrphy_training(phy_base, training_sequence);  in ddrphy_training()
546 	void __iomem *phy_base = umc_ch_base + 0x00030000;  in umc_ch_init()  local
557 	ddrphy_init(phy_base, freq, width, ch);  in umc_ch_init()
559 	ret = ddrphy_impedance_calibration(phy_base);  in umc_ch_init()
563 	ddrphy_dram_init(phy_base);  in umc_ch_init()
573 	ret = ddrphy_training(phy_base);  in umc_ch_init()
581 			       ddrphy_get_system_latency(phy_base, width));  in umc_ch_init()
587 	ddrphy_fifo_reset(phy_base);  in umc_ch_init()