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Searched refs:div_mask (Results 1 – 25 of 34) sorted by relevance

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/OK3568_Linux_fs/kernel/drivers/clk/imx/
H A Dclk-pllv3.c51 u32 div_mask; member
114 u32 div = (readl_relaxed(pll->base) >> pll->div_shift) & pll->div_mask; in clk_pllv3_recalc_rate()
142 val &= ~(pll->div_mask << pll->div_shift); in clk_pllv3_set_rate()
162 u32 div = readl_relaxed(pll->base) & pll->div_mask; in clk_pllv3_sys_recalc_rate()
197 val &= ~pll->div_mask; in clk_pllv3_sys_set_rate()
219 u32 div = readl_relaxed(pll->base) & pll->div_mask; in clk_pllv3_av_recalc_rate()
284 val &= ~pll->div_mask; in clk_pllv3_av_set_rate()
352 mf.mfi = (readl_relaxed(pll->base) & pll->div_mask) ? 22 : 20; in clk_pllv3_vf610_recalc_rate()
375 val &= ~pll->div_mask; /* clear bit for mfi=20 */ in clk_pllv3_vf610_set_rate()
377 val |= pll->div_mask; /* set bit for mfi=22 */ in clk_pllv3_vf610_set_rate()
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H A Dclk-fixup-div.c12 #define div_mask(d) ((1 << (d->width)) - 1) macro
66 if (value > div_mask(div)) in clk_fixup_div_set_rate()
67 value = div_mask(div); in clk_fixup_div_set_rate()
72 val &= ~(div_mask(div) << div->shift); in clk_fixup_div_set_rate()
H A Dclk.h75 #define imx_clk_pllv3(type, name, parent_name, base, div_mask) \ argument
76 to_clk(imx_clk_hw_pllv3(type, name, parent_name, base, div_mask))
177 const char *parent_name, void __iomem *base, u32 div_mask);
/OK3568_Linux_fs/kernel/drivers/clk/rockchip/
H A Dclk-half-divider.c11 #define div_mask(width) ((1 << (width)) - 1) macro
29 val &= div_mask(divider->width); in clk_half_divider_recalc_rate()
46 maxdiv = div_mask(width); in clk_half_divider_bestdiv()
80 bestdiv = div_mask(width); in clk_half_divider_bestdiv()
110 value = min_t(unsigned int, value, div_mask(divider->width)); in clk_half_divider_set_rate()
118 val = div_mask(divider->width) << (divider->shift + 16); in clk_half_divider_set_rate()
121 val &= ~(div_mask(divider->width) << divider->shift); in clk_half_divider_set_rate()
H A Dclk-dclk-divider.c13 #define div_mask(width) ((1 << (width)) - 1) macro
22 val &= div_mask(divider->width); in clk_dclk_recalc_rate()
31 int div, maxdiv = div_mask(divider->width) + 1; in clk_dclk_round_rate()
58 val = div_mask(divider->width) << (divider->shift + 16); in clk_dclk_set_rate()
61 val &= ~(div_mask(divider->width) << divider->shift); in clk_dclk_set_rate()
H A Dclk-pvtm.c34 u32 div_mask; member
141 if (div > pvtm->info->div_mask) { in rockchip_clock_pvtm_init_freq()
143 div = pvtm->info->div_mask; in rockchip_clock_pvtm_init_freq()
149 pvtm->info->div_mask)); in rockchip_clock_pvtm_init_freq()
205 .div_mask = 0x3f,
/OK3568_Linux_fs/kernel/drivers/clk/tegra/
H A Dclk-utils.c10 #define div_mask(w) ((1 << (w)) - 1) macro
39 if (divider_ux1 > div_mask(width)) in div_frac_get()
40 return div_mask(width); in div_frac_get()
H A Dclk-divider.c15 #define div_mask(d) ((1 << (d->width)) - 1) macro
17 #define get_max_div(d) div_mask(d)
49 div = (reg >> divider->shift) & div_mask(divider); in clk_frac_div_recalc_rate()
96 val &= ~(div_mask(divider) << divider->shift); in clk_frac_div_set_rate()
/OK3568_Linux_fs/u-boot/drivers/clk/rockchip/
H A Dclk_rk3528.c1051 u32 div_mask, div_shift; in rk3528_dclk_vop_get_clk() local
1062 div_mask = DCLK_VOP_SRC0_DIV_MASK; in rk3528_dclk_vop_get_clk()
1070 div_mask = DCLK_VOP_SRC1_DIV_MASK; in rk3528_dclk_vop_get_clk()
1079 div = (con & div_mask) >> div_shift; in rk3528_dclk_vop_get_clk()
1093 u32 div_mask, div_shift; in rk3528_dclk_vop_set_clk() local
1104 div_mask = DCLK_VOP_SRC0_DIV_MASK; in rk3528_dclk_vop_set_clk()
1112 div_mask = DCLK_VOP_SRC1_DIV_MASK; in rk3528_dclk_vop_set_clk()
1128 div = ((DIV_ROUND_UP(prate, rate) - 1) << div_shift) & div_mask; in rk3528_dclk_vop_set_clk()
1137 u32 sel_shift, sel_mask, div_shift, div_mask; in rk3528_uart_get_rate() local
1147 div_mask = CLK_UART0_SRC_DIV_MASK; in rk3528_uart_get_rate()
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/OK3568_Linux_fs/kernel/drivers/clk/
H A Dclk-vt8500.c23 unsigned int div_mask; member
118 u32 div = readl(cdev->div_reg) & cdev->div_mask; in vt8500_dclk_recalc_rate()
121 if ((cdev->div_mask == 0x3F) && (div & BIT(5))) in vt8500_dclk_recalc_rate()
126 div = (cdev->div_mask + 1); in vt8500_dclk_recalc_rate()
150 if ((cdev->div_mask == 0x3F) && (divisor > 31)) { in vt8500_dclk_round_rate()
169 if (divisor == cdev->div_mask + 1) in vt8500_dclk_set_rate()
173 if ((cdev->div_mask == 0x3F) && (divisor > 31)) { in vt8500_dclk_set_rate()
181 if (divisor > cdev->div_mask) { in vt8500_dclk_set_rate()
262 dev_clk->div_mask = 0x1f; in vtwm_device_clk_init()
264 of_property_read_u32(node, "divisor-mask", &dev_clk->div_mask); in vtwm_device_clk_init()
/OK3568_Linux_fs/kernel/drivers/i2c/busses/
H A Di2c-brcmstb.c94 u32 div_mask; member
126 .div_mask = 0
131 .div_mask = 0
136 .div_mask = 0
141 .div_mask = 0
146 .div_mask = BSC_CTL_REG_DIV_CLK_MASK
151 .div_mask = BSC_CTL_REG_DIV_CLK_MASK
156 .div_mask = BSC_CTL_REG_DIV_CLK_MASK
161 .div_mask = BSC_CTL_REG_DIV_CLK_MASK
555 bsc_clk[i].div_mask); in brcmstb_i2c_set_bus_speed()
/OK3568_Linux_fs/kernel/drivers/clk/hisilicon/
H A Dclkdivider-hi6220.c19 #define div_mask(width) ((1 << (width)) - 1) macro
52 val &= div_mask(dclk->width); in hi6220_clkdiv_recalc_rate()
82 data &= ~(div_mask(dclk->width) << dclk->shift); in hi6220_clkdiv_set_rate()
117 max_div = div_mask(width) + 1; in hi6220_register_clkdiv()
/OK3568_Linux_fs/kernel/include/linux/
H A Dsh_clk.h60 unsigned int div_mask; member
157 .div_mask = SH_CLK_DIV4_MSK, \
181 .div_mask = SH_CLK_DIV6_MSK, \
193 .div_mask = SH_CLK_DIV6_MSK, \
/OK3568_Linux_fs/kernel/drivers/clk/actions/
H A Dowl-factor.c158 val &= div_mask(factor_hw); in owl_factor_helper_recalc_rate()
193 if (val > div_mask(factor_hw)) in owl_factor_helper_set_rate()
194 val = div_mask(factor_hw); in owl_factor_helper_set_rate()
198 reg &= ~(div_mask(factor_hw) << factor_hw->shift); in owl_factor_helper_set_rate()
H A Dowl-factor.h58 #define div_mask(d) ((1 << ((d)->width)) - 1) macro
/OK3568_Linux_fs/kernel/drivers/clk/rockchip/regmap/
H A Dclk-regmap-divider.c20 #define div_mask(width) ((1 << (width)) - 1) macro
34 div &= div_mask(divider->width); in clk_regmap_divider_recalc_rate()
76 val = div_mask(divider->width) << (divider->shift + 16); in clk_regmap_divider_set_rate()
/OK3568_Linux_fs/kernel/drivers/clk/samsung/
H A Dclk-cpu.c230 unsigned long div = 0, div_mask = DIV_MASK; in exynos_cpuclk_post_rate_change() local
252 div_mask |= E4210_DIV0_ATB_MASK; in exynos_cpuclk_post_rate_change()
255 exynos_set_safe_div(base, div, div_mask); in exynos_cpuclk_post_rate_change()
340 unsigned long div = 0, div_mask = DIV_MASK; in exynos5433_cpuclk_post_rate_change() local
351 exynos5433_set_safe_div(base, div, div_mask); in exynos5433_cpuclk_post_rate_change()
/OK3568_Linux_fs/kernel/drivers/sh/clk/
H A Dcpg.c123 idx = (sh_clk_read(clk) >> clk->enable_bit) & clk->div_mask; in sh_clk_div_recalc()
139 value &= ~(clk->div_mask << clk->enable_bit); in sh_clk_div_set_rate()
152 if (clk->div_mask == SH_CLK_DIV6_MSK) { in sh_clk_div_enable()
175 val |= clk->div_mask; in sh_clk_div_disable()
/OK3568_Linux_fs/kernel/drivers/clk/at91/
H A Dclk-peripheral.c170 periph->layout->div_mask | periph->layout->cmd | in clk_sam9x5_peripheral_enable()
172 field_prep(periph->layout->div_mask, periph->div) | in clk_sam9x5_peripheral_enable()
233 periph->div = field_get(periph->layout->div_mask, status); in clk_sam9x5_peripheral_recalc_rate()
450 if (layout->div_mask) in at91_clk_register_sam9x5_peripheral()
H A Dpmc.h59 u32 div_mask; member
96 u32 div_mask; member
H A Dclk-sam9x60-pll.c253 cdiv = (val & core->layout->div_mask) >> core->layout->div_shift; in sam9x60_div_pll_prepare()
260 core->layout->div_mask | core->layout->endiv_mask, in sam9x60_div_pll_prepare()
343 for (divid = 1; divid < core->layout->div_mask; divid++) { in sam9x60_div_pll_compute_div()
/OK3568_Linux_fs/kernel/drivers/clk/mmp/
H A Dclk-mix.c29 unsigned int div_mask = (1 << mix->reg_info.width_div) - 1; in _get_maxdiv() local
34 return div_mask; in _get_maxdiv()
36 return 1 << div_mask; in _get_maxdiv()
43 return div_mask + 1; in _get_maxdiv()
/OK3568_Linux_fs/u-boot/arch/arm/mach-exynos/
H A Dclock.c24 int32_t div_mask; member
453 div = (div >> bit_info->div_bit) & bit_info->div_mask; in exynos5_get_periph_rate()
547 div = (div >> bit_info->div_bit) & bit_info->div_mask; in exynos542x_get_periph_rate()
1504 unsigned div_mask = 0xf, pre_div_mask = 0xff; in exynos5420_set_spi_clk() local
1554 clrsetbits_le32(reg, div_mask << shift, (main & div_mask) << shift); in exynos5420_set_spi_clk()
/OK3568_Linux_fs/kernel/drivers/clk/nxp/
H A Dclk-lpc32xx.c920 #define div_mask(width) ((1 << (width)) - 1) macro
952 val &= div_mask(divider->width); in clk_divider_recalc_rate()
968 bestdiv &= div_mask(divider->width); in clk_divider_round_rate()
988 div_mask(divider->width) << divider->shift, in clk_divider_set_rate()
1475 static void __init lpc32xx_clk_div_quirk(u32 reg, u32 div_mask, u32 gate) in lpc32xx_clk_div_quirk() argument
1481 if (!(val & div_mask)) { in lpc32xx_clk_div_quirk()
1483 val |= BIT(__ffs(div_mask)); in lpc32xx_clk_div_quirk()
1486 regmap_update_bits(clk_regmap, reg, gate | div_mask, val); in lpc32xx_clk_div_quirk()
/OK3568_Linux_fs/kernel/drivers/mfd/
H A Ddb8500-prcmu.c523 u32 div_mask; member
530 .div_mask = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_MASK,
535 .div_mask = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_MASK,
540 .div_mask = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_MASK,
646 u32 div_mask; in prcmu_config_clkout() local
656 div_mask = PRCM_CLKOCR_CLKODIV0_MASK; in prcmu_config_clkout()
661 div_mask = PRCM_CLKOCR_CLKODIV1_MASK; in prcmu_config_clkout()
672 if (val & div_mask) { in prcmu_config_clkout()
679 if ((val & mask & ~div_mask) != bits) { in prcmu_config_clkout()
1535 div = ((div & dsiescclk[n].div_mask) >> (dsiescclk[n].div_shift)); in dsiescclk_rate()
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