Lines Matching refs:div_mask
1051 u32 div_mask, div_shift; in rk3528_dclk_vop_get_clk() local
1062 div_mask = DCLK_VOP_SRC0_DIV_MASK; in rk3528_dclk_vop_get_clk()
1070 div_mask = DCLK_VOP_SRC1_DIV_MASK; in rk3528_dclk_vop_get_clk()
1079 div = (con & div_mask) >> div_shift; in rk3528_dclk_vop_get_clk()
1093 u32 div_mask, div_shift; in rk3528_dclk_vop_set_clk() local
1104 div_mask = DCLK_VOP_SRC0_DIV_MASK; in rk3528_dclk_vop_set_clk()
1112 div_mask = DCLK_VOP_SRC1_DIV_MASK; in rk3528_dclk_vop_set_clk()
1128 div = ((DIV_ROUND_UP(prate, rate) - 1) << div_shift) & div_mask; in rk3528_dclk_vop_set_clk()
1137 u32 sel_shift, sel_mask, div_shift, div_mask; in rk3528_uart_get_rate() local
1147 div_mask = CLK_UART0_SRC_DIV_MASK; in rk3528_uart_get_rate()
1155 div_mask = CLK_UART1_SRC_DIV_MASK; in rk3528_uart_get_rate()
1163 div_mask = CLK_UART2_SRC_DIV_MASK; in rk3528_uart_get_rate()
1171 div_mask = CLK_UART3_SRC_DIV_MASK; in rk3528_uart_get_rate()
1179 div_mask = CLK_UART4_SRC_DIV_MASK; in rk3528_uart_get_rate()
1187 div_mask = CLK_UART5_SRC_DIV_MASK; in rk3528_uart_get_rate()
1195 div_mask = CLK_UART6_SRC_DIV_MASK; in rk3528_uart_get_rate()
1203 div_mask = CLK_UART7_SRC_DIV_MASK; in rk3528_uart_get_rate()
1211 div = (con & div_mask) >> div_shift; in rk3528_uart_get_rate()
1234 u32 sel_shift, sel_mask, div_shift, div_mask; in rk3528_uart_set_rate() local
1259 div_mask = CLK_UART0_SRC_DIV_MASK; in rk3528_uart_set_rate()
1267 div_mask = CLK_UART1_SRC_DIV_MASK; in rk3528_uart_set_rate()
1275 div_mask = CLK_UART2_SRC_DIV_MASK; in rk3528_uart_set_rate()
1283 div_mask = CLK_UART3_SRC_DIV_MASK; in rk3528_uart_set_rate()
1291 div_mask = CLK_UART4_SRC_DIV_MASK; in rk3528_uart_set_rate()
1299 div_mask = CLK_UART5_SRC_DIV_MASK; in rk3528_uart_set_rate()
1307 div_mask = CLK_UART6_SRC_DIV_MASK; in rk3528_uart_set_rate()
1315 div_mask = CLK_UART7_SRC_DIV_MASK; in rk3528_uart_set_rate()
1322 rk_clrsetreg(&cru->clksel_con[id - 2], div_mask, (div - 1) << div_shift); in rk3528_uart_set_rate()