xref: /OK3568_Linux_fs/kernel/drivers/clk/rockchip/regmap/clk-regmap-divider.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * Copyright (c) 2017 Rockchip Electronics Co. Ltd.
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * Base on code in drivers/clk/clk-divider.c.
5*4882a593Smuzhiyun  * See clk-divider.c for further copyright information.
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * This program is free software; you can redistribute it and/or modify
8*4882a593Smuzhiyun  * it under the terms of the GNU General Public License as published by
9*4882a593Smuzhiyun  * the Free Software Foundation; either version 2 of the License, or
10*4882a593Smuzhiyun  * (at your option) any later version.
11*4882a593Smuzhiyun  *
12*4882a593Smuzhiyun  * This program is distributed in the hope that it will be useful,
13*4882a593Smuzhiyun  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14*4882a593Smuzhiyun  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15*4882a593Smuzhiyun  * GNU General Public License for more details.
16*4882a593Smuzhiyun  */
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun #include "clk-regmap.h"
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun #define div_mask(width)	((1 << (width)) - 1)
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun #define to_clk_regmap_divider(_hw)	\
23*4882a593Smuzhiyun 		container_of(_hw, struct clk_regmap_divider, hw)
24*4882a593Smuzhiyun 
25*4882a593Smuzhiyun static unsigned long
clk_regmap_divider_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)26*4882a593Smuzhiyun clk_regmap_divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
27*4882a593Smuzhiyun {
28*4882a593Smuzhiyun 	struct clk_regmap_divider *divider = to_clk_regmap_divider(hw);
29*4882a593Smuzhiyun 	unsigned int val, div;
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun 	regmap_read(divider->regmap, divider->reg, &val);
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun 	div = val >> divider->shift;
34*4882a593Smuzhiyun 	div &= div_mask(divider->width);
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun 	return divider_recalc_rate(hw, parent_rate, div, NULL,
37*4882a593Smuzhiyun 				   CLK_DIVIDER_ROUND_CLOSEST, divider->width);
38*4882a593Smuzhiyun }
39*4882a593Smuzhiyun 
40*4882a593Smuzhiyun static long
clk_regmap_divider_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate)41*4882a593Smuzhiyun clk_regmap_divider_round_rate(struct clk_hw *hw, unsigned long rate,
42*4882a593Smuzhiyun 			      unsigned long *prate)
43*4882a593Smuzhiyun {
44*4882a593Smuzhiyun 	struct clk_regmap_divider *divider = to_clk_regmap_divider(hw);
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun 	return divider_round_rate(hw, rate, prate, NULL, divider->width,
47*4882a593Smuzhiyun 				  CLK_DIVIDER_ROUND_CLOSEST);
48*4882a593Smuzhiyun }
49*4882a593Smuzhiyun 
div_round_closest(unsigned long parent_rate,unsigned long rate)50*4882a593Smuzhiyun static int div_round_closest(unsigned long parent_rate, unsigned long rate)
51*4882a593Smuzhiyun {
52*4882a593Smuzhiyun 	int up, down;
53*4882a593Smuzhiyun 	unsigned long up_rate, down_rate;
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun 	up = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
56*4882a593Smuzhiyun 	down = parent_rate / rate;
57*4882a593Smuzhiyun 
58*4882a593Smuzhiyun 	up_rate = DIV_ROUND_UP_ULL((u64)parent_rate, up);
59*4882a593Smuzhiyun 	down_rate = DIV_ROUND_UP_ULL((u64)parent_rate, down);
60*4882a593Smuzhiyun 
61*4882a593Smuzhiyun 	return (rate - up_rate) <= (down_rate - rate) ? up : down;
62*4882a593Smuzhiyun }
63*4882a593Smuzhiyun 
64*4882a593Smuzhiyun static int
clk_regmap_divider_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)65*4882a593Smuzhiyun clk_regmap_divider_set_rate(struct clk_hw *hw, unsigned long rate,
66*4882a593Smuzhiyun 			    unsigned long parent_rate)
67*4882a593Smuzhiyun {
68*4882a593Smuzhiyun 	struct clk_regmap_divider *divider = to_clk_regmap_divider(hw);
69*4882a593Smuzhiyun 	u32 val, div;
70*4882a593Smuzhiyun 
71*4882a593Smuzhiyun 	div = div_round_closest(parent_rate, rate);
72*4882a593Smuzhiyun 
73*4882a593Smuzhiyun 	dev_dbg(divider->dev, "%s: parent_rate=%ld, div=%d, rate=%ld\n",
74*4882a593Smuzhiyun 		clk_hw_get_name(hw), parent_rate, div, rate);
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun 	val = div_mask(divider->width) << (divider->shift + 16);
77*4882a593Smuzhiyun 	val |= (div - 1) << divider->shift;
78*4882a593Smuzhiyun 
79*4882a593Smuzhiyun 	return regmap_write(divider->regmap, divider->reg, val);
80*4882a593Smuzhiyun }
81*4882a593Smuzhiyun 
82*4882a593Smuzhiyun const struct clk_ops clk_regmap_divider_ops = {
83*4882a593Smuzhiyun 	.recalc_rate = clk_regmap_divider_recalc_rate,
84*4882a593Smuzhiyun 	.round_rate = clk_regmap_divider_round_rate,
85*4882a593Smuzhiyun 	.set_rate = clk_regmap_divider_set_rate,
86*4882a593Smuzhiyun };
87*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(clk_regmap_divider_ops);
88*4882a593Smuzhiyun 
89*4882a593Smuzhiyun struct clk *
devm_clk_regmap_register_divider(struct device * dev,const char * name,const char * parent_name,struct regmap * regmap,u32 reg,u8 shift,u8 width,unsigned long flags)90*4882a593Smuzhiyun devm_clk_regmap_register_divider(struct device *dev, const char *name,
91*4882a593Smuzhiyun 				 const char *parent_name, struct regmap *regmap,
92*4882a593Smuzhiyun 				 u32 reg, u8 shift, u8 width,
93*4882a593Smuzhiyun 				 unsigned long flags)
94*4882a593Smuzhiyun {
95*4882a593Smuzhiyun 	struct clk_regmap_divider *divider;
96*4882a593Smuzhiyun 	struct clk_init_data init = {};
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun 	divider = devm_kzalloc(dev, sizeof(*divider), GFP_KERNEL);
99*4882a593Smuzhiyun 	if (!divider)
100*4882a593Smuzhiyun 		return ERR_PTR(-ENOMEM);
101*4882a593Smuzhiyun 
102*4882a593Smuzhiyun 	init.name = name;
103*4882a593Smuzhiyun 	init.ops = &clk_regmap_divider_ops;
104*4882a593Smuzhiyun 	init.flags = flags;
105*4882a593Smuzhiyun 	init.parent_names = (parent_name ? &parent_name : NULL);
106*4882a593Smuzhiyun 	init.num_parents = (parent_name ? 1 : 0);
107*4882a593Smuzhiyun 
108*4882a593Smuzhiyun 	divider->dev = dev;
109*4882a593Smuzhiyun 	divider->regmap = regmap;
110*4882a593Smuzhiyun 	divider->reg = reg;
111*4882a593Smuzhiyun 	divider->shift = shift;
112*4882a593Smuzhiyun 	divider->width = width;
113*4882a593Smuzhiyun 	divider->hw.init = &init;
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun 	return devm_clk_register(dev, &divider->hw);
116*4882a593Smuzhiyun }
117*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(devm_clk_regmap_register_divider);
118