1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2013 Freescale Semiconductor, Inc.
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #include <linux/clk-provider.h>
7*4882a593Smuzhiyun #include <linux/err.h>
8*4882a593Smuzhiyun #include <linux/io.h>
9*4882a593Smuzhiyun #include <linux/slab.h>
10*4882a593Smuzhiyun #include "clk.h"
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #define div_mask(d) ((1 << (d->width)) - 1)
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun /**
15*4882a593Smuzhiyun * struct clk_fixup_div - imx integer fixup divider clock
16*4882a593Smuzhiyun * @divider: the parent class
17*4882a593Smuzhiyun * @ops: pointer to clk_ops of parent class
18*4882a593Smuzhiyun * @fixup: a hook to fixup the write value
19*4882a593Smuzhiyun *
20*4882a593Smuzhiyun * The imx fixup divider clock is a subclass of basic clk_divider
21*4882a593Smuzhiyun * with an addtional fixup hook.
22*4882a593Smuzhiyun */
23*4882a593Smuzhiyun struct clk_fixup_div {
24*4882a593Smuzhiyun struct clk_divider divider;
25*4882a593Smuzhiyun const struct clk_ops *ops;
26*4882a593Smuzhiyun void (*fixup)(u32 *val);
27*4882a593Smuzhiyun };
28*4882a593Smuzhiyun
to_clk_fixup_div(struct clk_hw * hw)29*4882a593Smuzhiyun static inline struct clk_fixup_div *to_clk_fixup_div(struct clk_hw *hw)
30*4882a593Smuzhiyun {
31*4882a593Smuzhiyun struct clk_divider *divider = to_clk_divider(hw);
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun return container_of(divider, struct clk_fixup_div, divider);
34*4882a593Smuzhiyun }
35*4882a593Smuzhiyun
clk_fixup_div_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)36*4882a593Smuzhiyun static unsigned long clk_fixup_div_recalc_rate(struct clk_hw *hw,
37*4882a593Smuzhiyun unsigned long parent_rate)
38*4882a593Smuzhiyun {
39*4882a593Smuzhiyun struct clk_fixup_div *fixup_div = to_clk_fixup_div(hw);
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun return fixup_div->ops->recalc_rate(&fixup_div->divider.hw, parent_rate);
42*4882a593Smuzhiyun }
43*4882a593Smuzhiyun
clk_fixup_div_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate)44*4882a593Smuzhiyun static long clk_fixup_div_round_rate(struct clk_hw *hw, unsigned long rate,
45*4882a593Smuzhiyun unsigned long *prate)
46*4882a593Smuzhiyun {
47*4882a593Smuzhiyun struct clk_fixup_div *fixup_div = to_clk_fixup_div(hw);
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun return fixup_div->ops->round_rate(&fixup_div->divider.hw, rate, prate);
50*4882a593Smuzhiyun }
51*4882a593Smuzhiyun
clk_fixup_div_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)52*4882a593Smuzhiyun static int clk_fixup_div_set_rate(struct clk_hw *hw, unsigned long rate,
53*4882a593Smuzhiyun unsigned long parent_rate)
54*4882a593Smuzhiyun {
55*4882a593Smuzhiyun struct clk_fixup_div *fixup_div = to_clk_fixup_div(hw);
56*4882a593Smuzhiyun struct clk_divider *div = to_clk_divider(hw);
57*4882a593Smuzhiyun unsigned int divider, value;
58*4882a593Smuzhiyun unsigned long flags;
59*4882a593Smuzhiyun u32 val;
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun divider = parent_rate / rate;
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun /* Zero based divider */
64*4882a593Smuzhiyun value = divider - 1;
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun if (value > div_mask(div))
67*4882a593Smuzhiyun value = div_mask(div);
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun spin_lock_irqsave(div->lock, flags);
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun val = readl(div->reg);
72*4882a593Smuzhiyun val &= ~(div_mask(div) << div->shift);
73*4882a593Smuzhiyun val |= value << div->shift;
74*4882a593Smuzhiyun fixup_div->fixup(&val);
75*4882a593Smuzhiyun writel(val, div->reg);
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun spin_unlock_irqrestore(div->lock, flags);
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun return 0;
80*4882a593Smuzhiyun }
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun static const struct clk_ops clk_fixup_div_ops = {
83*4882a593Smuzhiyun .recalc_rate = clk_fixup_div_recalc_rate,
84*4882a593Smuzhiyun .round_rate = clk_fixup_div_round_rate,
85*4882a593Smuzhiyun .set_rate = clk_fixup_div_set_rate,
86*4882a593Smuzhiyun };
87*4882a593Smuzhiyun
imx_clk_hw_fixup_divider(const char * name,const char * parent,void __iomem * reg,u8 shift,u8 width,void (* fixup)(u32 * val))88*4882a593Smuzhiyun struct clk_hw *imx_clk_hw_fixup_divider(const char *name, const char *parent,
89*4882a593Smuzhiyun void __iomem *reg, u8 shift, u8 width,
90*4882a593Smuzhiyun void (*fixup)(u32 *val))
91*4882a593Smuzhiyun {
92*4882a593Smuzhiyun struct clk_fixup_div *fixup_div;
93*4882a593Smuzhiyun struct clk_hw *hw;
94*4882a593Smuzhiyun struct clk_init_data init;
95*4882a593Smuzhiyun int ret;
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun if (!fixup)
98*4882a593Smuzhiyun return ERR_PTR(-EINVAL);
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun fixup_div = kzalloc(sizeof(*fixup_div), GFP_KERNEL);
101*4882a593Smuzhiyun if (!fixup_div)
102*4882a593Smuzhiyun return ERR_PTR(-ENOMEM);
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun init.name = name;
105*4882a593Smuzhiyun init.ops = &clk_fixup_div_ops;
106*4882a593Smuzhiyun init.flags = CLK_SET_RATE_PARENT;
107*4882a593Smuzhiyun init.parent_names = parent ? &parent : NULL;
108*4882a593Smuzhiyun init.num_parents = parent ? 1 : 0;
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun fixup_div->divider.reg = reg;
111*4882a593Smuzhiyun fixup_div->divider.shift = shift;
112*4882a593Smuzhiyun fixup_div->divider.width = width;
113*4882a593Smuzhiyun fixup_div->divider.lock = &imx_ccm_lock;
114*4882a593Smuzhiyun fixup_div->divider.hw.init = &init;
115*4882a593Smuzhiyun fixup_div->ops = &clk_divider_ops;
116*4882a593Smuzhiyun fixup_div->fixup = fixup;
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun hw = &fixup_div->divider.hw;
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun ret = clk_hw_register(NULL, hw);
121*4882a593Smuzhiyun if (ret) {
122*4882a593Smuzhiyun kfree(fixup_div);
123*4882a593Smuzhiyun return ERR_PTR(ret);
124*4882a593Smuzhiyun }
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun return hw;
127*4882a593Smuzhiyun }
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