1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #include <asm/div64.h>
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include "clk.h"
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #define div_mask(w) ((1 << (w)) - 1)
11*4882a593Smuzhiyun
div_frac_get(unsigned long rate,unsigned parent_rate,u8 width,u8 frac_width,u8 flags)12*4882a593Smuzhiyun int div_frac_get(unsigned long rate, unsigned parent_rate, u8 width,
13*4882a593Smuzhiyun u8 frac_width, u8 flags)
14*4882a593Smuzhiyun {
15*4882a593Smuzhiyun u64 divider_ux1 = parent_rate;
16*4882a593Smuzhiyun int mul;
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun if (!rate)
19*4882a593Smuzhiyun return 0;
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun mul = 1 << frac_width;
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun if (!(flags & TEGRA_DIVIDER_INT))
24*4882a593Smuzhiyun divider_ux1 *= mul;
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun if (flags & TEGRA_DIVIDER_ROUND_UP)
27*4882a593Smuzhiyun divider_ux1 += rate - 1;
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun do_div(divider_ux1, rate);
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun if (flags & TEGRA_DIVIDER_INT)
32*4882a593Smuzhiyun divider_ux1 *= mul;
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun if (divider_ux1 < mul)
35*4882a593Smuzhiyun return 0;
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun divider_ux1 -= mul;
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun if (divider_ux1 > div_mask(width))
40*4882a593Smuzhiyun return div_mask(width);
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun return divider_ux1;
43*4882a593Smuzhiyun }
44