Home
last modified time | relevance | path

Searched refs:clk_base (Results 1 – 25 of 29) sorted by relevance

12

/OK3568_Linux_fs/kernel/drivers/clk/tegra/
H A Dclk-tegra210.c298 static void __iomem *clk_base; variable
496 val = readl_relaxed(clk_base + XUSBIO_PLL_CFG0); in tegra210_xusb_pll_hw_control_enable()
501 writel_relaxed(val, clk_base + XUSBIO_PLL_CFG0); in tegra210_xusb_pll_hw_control_enable()
509 val = readl_relaxed(clk_base + XUSBIO_PLL_CFG0); in tegra210_xusb_pll_hw_sequence_start()
511 writel_relaxed(val, clk_base + XUSBIO_PLL_CFG0); in tegra210_xusb_pll_hw_sequence_start()
519 val = readl_relaxed(clk_base + SATA_PLL_CFG0); in tegra210_sata_pll_hw_control_enable()
523 writel_relaxed(val, clk_base + SATA_PLL_CFG0); in tegra210_sata_pll_hw_control_enable()
531 val = readl_relaxed(clk_base + SATA_PLL_CFG0); in tegra210_sata_pll_hw_sequence_start()
533 writel_relaxed(val, clk_base + SATA_PLL_CFG0); in tegra210_sata_pll_hw_sequence_start()
541 val = readl_relaxed(clk_base + SATA_PLL_CFG0); in tegra210_set_sata_pll_seq_sw()
[all …]
H A Dclk-tegra-super-gen4.c95 static void __init tegra_sclk_init(void __iomem *clk_base, in tegra_sclk_init() argument
109 clk_base + SCLK_BURST_POLICY, in tegra_sclk_init()
119 clk_base + SCLK_DIVIDER, 0, 8, in tegra_sclk_init()
132 clk_base + SCLK_BURST_POLICY, in tegra_sclk_init()
142 clk_base + SYSTEM_CLK_RATE, 4, 2, 0, in tegra_sclk_init()
146 clk_base + SYSTEM_CLK_RATE, in tegra_sclk_init()
157 clk_base + SYSTEM_CLK_RATE, 0, 2, 0, in tegra_sclk_init()
160 CLK_IS_CRITICAL, clk_base + SYSTEM_CLK_RATE, in tegra_sclk_init()
165 static void __init tegra_super_clk_init(void __iomem *clk_base, in tegra_super_clk_init() argument
182 clk_base + CCLKG_BURST_POLICY, in tegra_super_clk_init()
[all …]
H A Dclk-tegra20.c130 static void __iomem *clk_base; variable
572 u32 osc_ctrl = readl_relaxed(clk_base + OSC_CTRL); in tegra20_clk_measure_input_freq()
606 u32 pll_ref_div = readl_relaxed(clk_base + OSC_CTRL) & in tegra20_get_pll_ref_div()
628 clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, NULL, 0, in tegra20_pll_init()
634 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra20_pll_init()
637 clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT, in tegra20_pll_init()
642 clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, NULL, in tegra20_pll_init()
648 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra20_pll_init()
651 clk_base + PLLM_OUT, 1, 0, in tegra20_pll_init()
656 clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, NULL, 0, in tegra20_pll_init()
[all …]
H A Dclk-tegra30.c148 static void __iomem *clk_base; variable
816 clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, pmc_base, 0, in tegra30_pll_init()
822 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra30_pll_init()
825 clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT, in tegra30_pll_init()
830 clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, pmc_base, in tegra30_pll_init()
836 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra30_pll_init()
839 clk_base + PLLM_OUT, 1, 0, in tegra30_pll_init()
844 clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, pmc_base, 0, in tegra30_pll_init()
854 clk = tegra_clk_register_pllu("pll_u", "pll_ref", clk_base, 0, in tegra30_pll_init()
859 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc_base, 0, in tegra30_pll_init()
[all …]
H A Dclk-tegra114.c130 static void __iomem *clk_base; variable
890 static void __init tegra114_fixed_clk_init(void __iomem *clk_base) in tegra114_fixed_clk_init() argument
899 static void __init tegra114_pll_init(void __iomem *clk_base, in tegra114_pll_init() argument
905 clk = tegra_clk_register_pllxc("pll_c", "pll_ref", clk_base, in tegra114_pll_init()
911 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra114_pll_init()
914 clk_base + PLLC_OUT, 1, 0, in tegra114_pll_init()
919 clk = tegra_clk_register_pllc("pll_c2", "pll_ref", clk_base, pmc, 0, in tegra114_pll_init()
924 clk = tegra_clk_register_pllc("pll_c3", "pll_ref", clk_base, pmc, 0, in tegra114_pll_init()
929 clk = tegra_clk_register_pllm("pll_m", "pll_ref", clk_base, pmc, in tegra114_pll_init()
935 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra114_pll_init()
[all …]
H A Dclk.h379 void __iomem *clk_base; member
405 void __iomem *clk_base, void __iomem *pmc,
410 void __iomem *clk_base, void __iomem *pmc,
415 void __iomem *clk_base, void __iomem *pmc,
421 void __iomem *clk_base, void __iomem *pmc,
427 void __iomem *clk_base, void __iomem *pmc,
433 void __iomem *clk_base, void __iomem *pmc,
439 const char *parent_name, void __iomem *clk_base,
446 void __iomem *clk_base, unsigned long flags,
452 void __iomem *clk_base, unsigned long flags,
[all …]
H A Dclk-tegra124.c119 static void __iomem *clk_base; variable
1024 static __init void tegra124_periph_clk_init(void __iomem *clk_base, in tegra124_periph_clk_init() argument
1035 clk = tegra_clk_register_periph_fixed("dpaux", "pll_p", 0, clk_base, in tegra124_periph_clk_init()
1040 clk_base + PLLD_MISC, 30, 0, &pll_d_lock); in tegra124_periph_clk_init()
1044 clk_base, 0, 48, in tegra124_periph_clk_init()
1049 clk_base, 0, 82, in tegra124_periph_clk_init()
1053 clk = tegra_clk_register_mc("mc", "emc", clk_base + CLK_SOURCE_EMC, in tegra124_periph_clk_init()
1058 clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX, in tegra124_periph_clk_init()
1064 clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX, in tegra124_periph_clk_init()
1079 clk = tegra_clk_register_periph_data(clk_base, init); in tegra124_periph_clk_init()
[all …]
H A Dclk-periph-gate.c20 readl_relaxed(gate->clk_base + (gate->regs->enb_reg))
22 writel_relaxed(val, gate->clk_base + (gate->regs->enb_set_reg))
24 writel_relaxed(val, gate->clk_base + (gate->regs->enb_clr_reg))
27 readl_relaxed(gate->clk_base + (gate->regs->rst_reg))
29 writel_relaxed(val, gate->clk_base + (gate->regs->rst_clr_reg))
67 writel_relaxed(0, gate->clk_base + LVL2_CLK_GATE_OVRE); in clk_periph_enable_locked()
68 writel_relaxed(BIT(22), gate->clk_base + LVL2_CLK_GATE_OVRE); in clk_periph_enable_locked()
70 writel_relaxed(0, gate->clk_base + LVL2_CLK_GATE_OVRE); in clk_periph_enable_locked()
145 const char *parent_name, u8 gate_flags, void __iomem *clk_base, in tegra_clk_register_periph_gate() argument
170 gate->clk_base = clk_base; in tegra_clk_register_periph_gate()
H A Dclk-tegra-audio.c128 static void __init tegra_audio_sync_clk_init(void __iomem *clk_base, in tegra_audio_sync_clk_init() argument
148 clk_base + data->offset, 0, 3, 0, in tegra_audio_sync_clk_init()
157 0, clk_base + data->offset, 4, in tegra_audio_sync_clk_init()
163 void __init tegra_audio_clk_init(void __iomem *clk_base, in tegra_audio_clk_init() argument
184 clk_base, pmc_base, 0, info->pll_params, in tegra_audio_clk_init()
194 clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra_audio_clk_init()
197 clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED | in tegra_audio_clk_init()
215 tegra_audio_sync_clk_init(clk_base, tegra_clks, audio_clks, in tegra_audio_clk_init()
221 writel_relaxed(1, clk_base + dmic_clks[i].offset); in tegra_audio_clk_init()
223 tegra_audio_sync_clk_init(clk_base, tegra_clks, dmic_clks, in tegra_audio_clk_init()
[all …]
H A Dclk.c94 static void __iomem *clk_base; variable
110 clk_base + periph_regs[id / 32].rst_set_reg); in tegra_clk_rst_assert()
124 clk_base + periph_regs[id / 32].rst_clr_reg); in tegra_clk_rst_deassert()
163 val = readl_relaxed(clk_base + CLK_OUT_ENB_Y); in tegra_clk_set_pllp_out_cpu()
169 writel_relaxed(val, clk_base + CLK_OUT_ENB_Y); in tegra_clk_set_pllp_out_cpu()
179 readl_relaxed(clk_base + periph_regs[i].enb_reg); in tegra_clk_periph_suspend()
183 readl_relaxed(clk_base + periph_regs[i].rst_reg); in tegra_clk_periph_suspend()
193 clk_base + periph_regs[i].enb_reg); in tegra_clk_periph_resume()
199 fence_udelay(5, clk_base); in tegra_clk_periph_resume()
203 clk_base + periph_regs[i].rst_reg); in tegra_clk_periph_resume()
[all …]
H A Dclk-periph.c164 void __iomem *clk_base, u32 offset, in _tegra_clk_register_periph() argument
192 periph->mux.reg = clk_base + offset; in _tegra_clk_register_periph()
193 periph->divider.reg = div ? (clk_base + offset) : NULL; in _tegra_clk_register_periph()
194 periph->gate.clk_base = clk_base; in _tegra_clk_register_periph()
211 struct tegra_clk_periph *periph, void __iomem *clk_base, in tegra_clk_register_periph() argument
215 periph, clk_base, offset, flags); in tegra_clk_register_periph()
220 struct tegra_clk_periph *periph, void __iomem *clk_base, in tegra_clk_register_periph_nodiv() argument
225 periph, clk_base, offset, CLK_SET_RATE_PARENT); in tegra_clk_register_periph_nodiv()
228 struct clk *tegra_clk_register_periph_data(void __iomem *clk_base, in tegra_clk_register_periph_data() argument
233 clk_base, init->offset, init->flags); in tegra_clk_register_periph_data()
H A Dclk-tegra-fixed.c25 int __init tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks, in tegra_osc_clk_init() argument
35 val = readl_relaxed(clk_base + OSC_CTRL); in tegra_osc_clk_init()
110 void tegra_clk_osc_resume(void __iomem *clk_base) in tegra_clk_osc_resume() argument
114 val = readl_relaxed(clk_base + OSC_CTRL) & ~OSC_CTRL_MASK; in tegra_clk_osc_resume()
116 writel_relaxed(val, clk_base + OSC_CTRL); in tegra_clk_osc_resume()
117 fence_udelay(2, clk_base); in tegra_clk_osc_resume()
H A Dclk-pll.c230 #define pll_readl(offset, p) readl_relaxed(p->clk_base + offset)
237 #define pll_writel(val, offset, p) writel_relaxed(val, p->clk_base + offset)
302 lock_addr = pll->clk_base; in clk_pll_wait_for_lock()
999 val = readl(pll->clk_base + PLLE_SS_CTRL); in clk_plle_enable()
1002 writel(val, pll->clk_base + PLLE_SS_CTRL); in clk_plle_enable()
1159 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG2); in clk_pllu_enable()
1169 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG2); in clk_pllu_enable()
1171 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1); in clk_pllu_enable()
1181 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1); in clk_pllu_enable()
1265 void __iomem *clk_base, in _setup_dynamic_ramp() argument
[all …]
H A Dclk-tegra-periph.c864 static void __init periph_clk_init(void __iomem *clk_base, in periph_clk_init() argument
886 clk = tegra_clk_register_periph_data(clk_base, data); in periph_clk_init()
891 static void __init gate_clk_init(void __iomem *clk_base, in gate_clk_init() argument
909 clk_base, data->flags, in gate_clk_init()
916 static void __init div_clk_init(void __iomem *clk_base, in div_clk_init() argument
933 data->p.parent_name, clk_base + data->offset, in div_clk_init()
943 static void __init init_pllp(void __iomem *clk_base, void __iomem *pmc_base, in init_pllp() argument
954 clk = tegra_clk_register_pll("pll_p", "pll_ref", clk_base, in init_pllp()
970 clk_base + data->offset, 0, data->div_flags, in init_pllp()
973 data->div_name, clk_base + data->offset, in init_pllp()
[all …]
H A Dclk-sdmmc-mux.c235 void __iomem *clk_base, u32 offset, u32 clk_num, u8 div_flags, in tegra_clk_register_sdmmc_mux_div() argument
259 sdmmc_mux->reg = clk_base + offset; in tegra_clk_register_sdmmc_mux_div()
261 sdmmc_mux->gate.clk_base = clk_base; in tegra_clk_register_sdmmc_mux_div()
/OK3568_Linux_fs/kernel/arch/arm/mach-prima2/
H A Dplatsmp.c22 static void __iomem *clk_base; variable
59 clk_base = of_iomap(np, 0); in sirfsoc_boot_secondary()
60 if (!clk_base) in sirfsoc_boot_secondary()
71 clk_base + SIRFSOC_CPU1_JUMPADDR_OFFSET); in sirfsoc_boot_secondary()
75 clk_base + SIRFSOC_CPU1_WAKEMAGIC_OFFSET); in sirfsoc_boot_secondary()
/OK3568_Linux_fs/u-boot/board/hisilicon/hikey/
H A Dhikey.c150 void hi6220_clk_enable(u32 bitfield, unsigned int *clk_base) in hi6220_clk_enable() argument
154 data = readl(clk_base); in hi6220_clk_enable()
157 writel(bitfield, clk_base); in hi6220_clk_enable()
159 data = readl(clk_base + STAT_EN_OFF); in hi6220_clk_enable()
166 void hi6220_clk_disable(u32 bitfield, unsigned int *clk_base) in hi6220_clk_disable() argument
170 data = readl(clk_base); in hi6220_clk_disable()
173 writel(data, clk_base); in hi6220_clk_disable()
175 data = readl(clk_base + STAT_DIS_OFF); in hi6220_clk_disable()
/OK3568_Linux_fs/u-boot/board/freescale/t208xqds/
H A Dt208xqds.c380 int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]); in get_board_sys_clk()
418 int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]); in get_board_ddr_clk()
/OK3568_Linux_fs/kernel/drivers/clk/
H A Dclk-npcm7xx.c544 void __iomem *clk_base; in npcm7xx_clk_init() local
557 clk_base = ioremap(res.start, resource_size(&res)); in npcm7xx_clk_init()
558 if (!clk_base) in npcm7xx_clk_init()
575 hw = npcm7xx_clk_register_pll(clk_base + pll_data->reg, in npcm7xx_clk_init()
608 mux_data->flags, clk_base + NPCM7XX_CLKSEL, in npcm7xx_clk_init()
628 clk_base + div_data->reg, in npcm7xx_clk_init()
652 iounmap(clk_base); in npcm7xx_clk_init()
/OK3568_Linux_fs/u-boot/drivers/mmc/
H A Datmel_sdhci.c61 u32 clk_base, clk_mul; in atmel_sdhci_probe() local
82 clk_base = (caps & SDHCI_CLOCK_V3_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT; in atmel_sdhci_probe()
85 gck_rate = clk_base * 1000000 * (clk_mul + 1); in atmel_sdhci_probe()
/OK3568_Linux_fs/kernel/drivers/pinctrl/samsung/
H A Dpinctrl-exynos-arm.c45 void __iomem *clk_base = (void __iomem *)drvdata->retention_ctrl->priv; in s5pv210_retention_disable() local
48 tmp = __raw_readl(clk_base + S5P_OTHERS); in s5pv210_retention_disable()
51 __raw_writel(tmp, clk_base + S5P_OTHERS); in s5pv210_retention_disable()
60 void __iomem *clk_base; in s5pv210_retention_init() local
73 clk_base = of_iomap(np, 0); in s5pv210_retention_init()
75 if (!clk_base) { in s5pv210_retention_init()
80 ctrl->priv = (void __force *)clk_base; in s5pv210_retention_init()
/OK3568_Linux_fs/kernel/drivers/cpufreq/
H A Ds5pv210-cpufreq.c24 static void __iomem *clk_base; variable
27 #define S5P_CLKREG(x) (clk_base + (x))
624 clk_base = of_iomap(np, 0); in s5pv210_cpufreq_probe()
626 if (!clk_base) { in s5pv210_cpufreq_probe()
670 iounmap(clk_base); in s5pv210_cpufreq_probe()
/OK3568_Linux_fs/kernel/drivers/clk/nxp/
H A Dclk-lpc18xx-cgu.c638 static struct clk *clk_base[BASE_CLK_MAX]; variable
640 .clks = clk_base,
649 clk_base[i] = lpc18xx_register_base_clk(&lpc18xx_cgu_base_clks[i], in lpc18xx_cgu_register_base_clks()
651 if (IS_ERR(clk_base[i]) && PTR_ERR(clk_base[i]) != -ENOENT) in lpc18xx_cgu_register_base_clks()
/OK3568_Linux_fs/u-boot/board/freescale/t4qds/
H A Dt4240qds.c578 int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]); in get_board_sys_clk()
615 int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]); in get_board_ddr_clk()
/OK3568_Linux_fs/kernel/drivers/mmc/host/
H A Dsdhci-of-at91.c173 unsigned int clk_base, clk_mul; in sdhci_at91_set_clks_presets() local
187 clk_base = clk_base_rate / 1000000; in sdhci_at91_set_clks_presets()
191 caps0 |= FIELD_PREP(SDHCI_CLOCK_V3_BASE_MASK, clk_base); in sdhci_at91_set_clks_presets()

12