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Searched refs:__raw_readl (Results 1 – 25 of 594) sorted by relevance

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/OK3568_Linux_fs/kernel/arch/mips/sgi-ip22/
H A Dip22-nvram.c36 __raw_writel(__raw_readl(ptr) & ~EEPROM_DATO, ptr); \
37 __raw_writel(__raw_readl(ptr) & ~EEPROM_ECLK, ptr); \
38 __raw_writel(__raw_readl(ptr) & ~EEPROM_EPROT, ptr); \
40 __raw_writel(__raw_readl(ptr) | EEPROM_CSEL, ptr); \
41 __raw_writel(__raw_readl(ptr) | EEPROM_ECLK, ptr); })
45 __raw_writel(__raw_readl(ptr) & ~EEPROM_ECLK, ptr); \
46 __raw_writel(__raw_readl(ptr) & ~EEPROM_CSEL, ptr); \
47 __raw_writel(__raw_readl(ptr) | EEPROM_EPROT, ptr); \
48 __raw_writel(__raw_readl(ptr) | EEPROM_ECLK, ptr); })
64 __raw_writel(__raw_readl(ctrl) | EEPROM_DATO, ctrl); in eeprom_cmd()
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-keystone/
H A Dpsc.c54 ptstat = __raw_readl(KS2_PSC_BASE + PSC_REG_PSTAT); in psc_wait()
74 domain_num = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCFG(mod_num)); in psc_get_domain_num()
107 v = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCFG(mod_num)); in psc_set_state()
124 pdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_PDCTL(domain_num)); in psc_set_state()
131 mdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num)); in psc_set_state()
137 ptcmd = __raw_readl(KS2_PSC_BASE + PSC_REG_PTCMD); in psc_set_state()
161 mdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num)); in psc_enable_module()
179 mdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num)); in psc_disable_module()
205 mdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num)); in psc_set_reset_iso()
209 v = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCFG(mod_num)); in psc_set_reset_iso()
[all …]
H A Dddr3.c29 while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) in ddr3_init_ddrphy()
35 tmp = __raw_readl(base + KS2_DDRPHY_PGCR1_OFFSET); in ddr3_init_ddrphy()
45 tmp = __raw_readl(base + KS2_DDRPHY_DCR_OFFSET); in ddr3_init_ddrphy()
64 while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1) in ddr3_init_ddrphy()
98 while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1) in ddr3_init_ddrphy()
115 u32 value = __raw_readl(base + KS2_DDR3_MIDR_OFFSET); in ddr3_ecc_support_rmw()
134 data = __raw_readl(base + KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET); in ddr3_ecc_config()
332 u32 value = __raw_readl(base + KS2_DDR3_ECC_INT_STATUS_OFFSET); in ddr3_check_ecc_int()
350 value = __raw_readl(base + KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET); in ddr3_check_ecc_int()
353 value = __raw_readl(base + in ddr3_check_ecc_int()
[all …]
H A Dcmd_ddr3.c45 value = __raw_readl(index); in ddr_memory_test()
48 index, value, __raw_readl(index)); in ddr_memory_test()
71 value = __raw_readl(index); in ddr_memory_test()
74 index, value, __raw_readl(index)); in ddr_memory_test()
142 value = __raw_readl(index); in ddr_memory_compare()
143 value2 = __raw_readl(index2); in ddr_memory_compare()
164 value1 = __raw_readl(address); in ddr_memory_ecc_err()
168 value3 = __raw_readl(address); in ddr_memory_ecc_err()
178 value1 = __raw_readl(address); in ddr_memory_ecc_err()
/OK3568_Linux_fs/kernel/arch/mips/alchemy/common/
H A Dusb.c102 r = __raw_readl(base + USB_DWC_CTRL2); in __au1300_usb_phyctl()
103 s = __raw_readl(base + USB_DWC_CTRL3); in __au1300_usb_phyctl()
131 r = __raw_readl(base + USB_DWC_CTRL3); /* enable OHCI block */ in __au1300_ohci_control()
139 r = __raw_readl(base + USB_INT_ENABLE); in __au1300_ohci_control()
148 r = __raw_readl(base + USB_INT_ENABLE); in __au1300_ohci_control()
153 r = __raw_readl(base + USB_DWC_CTRL3); in __au1300_ohci_control()
168 r = __raw_readl(base + USB_DWC_CTRL3); in __au1300_ehci_control()
173 r = __raw_readl(base + USB_DWC_CTRL1); in __au1300_ehci_control()
180 r = __raw_readl(base + USB_INT_ENABLE); in __au1300_ehci_control()
185 r = __raw_readl(base + USB_INT_ENABLE); in __au1300_ehci_control()
[all …]
/OK3568_Linux_fs/kernel/arch/mips/loongson32/common/
H A Dirq.c28 __raw_writel(__raw_readl(LS1X_INTC_INTCLR(n)) in ls1x_irq_ack()
37 __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n)) in ls1x_irq_mask()
46 __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n)) in ls1x_irq_mask_ack()
48 __raw_writel(__raw_readl(LS1X_INTC_INTCLR(n)) in ls1x_irq_mask_ack()
57 __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n)) in ls1x_irq_unmask()
68 __raw_writel(__raw_readl(LS1X_INTC_INTPOL(n)) in ls1x_irq_settype()
70 __raw_writel(__raw_readl(LS1X_INTC_INTEDGE(n)) in ls1x_irq_settype()
74 __raw_writel(__raw_readl(LS1X_INTC_INTPOL(n)) in ls1x_irq_settype()
76 __raw_writel(__raw_readl(LS1X_INTC_INTEDGE(n)) in ls1x_irq_settype()
80 __raw_writel(__raw_readl(LS1X_INTC_INTPOL(n)) in ls1x_irq_settype()
[all …]
/OK3568_Linux_fs/kernel/arch/arm/mach-s3c/
H A Dpm-gpio.c29 chip->pm_save[0] = __raw_readl(chip->base + OFFS_CON); in samsung_gpio_pm_1bit_save()
30 chip->pm_save[1] = __raw_readl(chip->base + OFFS_DAT); in samsung_gpio_pm_1bit_save()
36 u32 old_gpcon = __raw_readl(base + OFFS_CON); in samsung_gpio_pm_1bit_resume()
37 u32 old_gpdat = __raw_readl(base + OFFS_DAT); in samsung_gpio_pm_1bit_resume()
66 chip->pm_save[0] = __raw_readl(chip->base + OFFS_CON); in samsung_gpio_pm_2bit_save()
67 chip->pm_save[1] = __raw_readl(chip->base + OFFS_DAT); in samsung_gpio_pm_2bit_save()
68 chip->pm_save[2] = __raw_readl(chip->base + OFFS_UP); in samsung_gpio_pm_2bit_save()
123 u32 old_gpcon = __raw_readl(base + OFFS_CON); in samsung_gpio_pm_2bit_resume()
124 u32 old_gpdat = __raw_readl(base + OFFS_DAT); in samsung_gpio_pm_2bit_resume()
194 chip->pm_save[1] = __raw_readl(chip->base + OFFS_CON); in samsung_gpio_pm_4bit_save()
[all …]
H A Dpm-core-s3c24xx.h20 unsigned long tmp = __raw_readl(S3C2410_CLKCON); in s3c_pm_debug_init_uart()
39 __raw_writel(__raw_readl(S3C2410_EINTPEND), S3C2410_EINTPEND); in s3c_pm_arch_prepare_irqs()
40 __raw_writel(__raw_readl(S3C2410_INTPND), S3C2410_INTPND); in s3c_pm_arch_prepare_irqs()
41 __raw_writel(__raw_readl(S3C2410_SRCPND), S3C2410_SRCPND); in s3c_pm_arch_prepare_irqs()
71 __raw_readl(S3C2410_SRCPND), in s3c_pm_arch_show_resume_irqs()
72 __raw_readl(S3C2410_EINTPEND)); in s3c_pm_arch_show_resume_irqs()
74 s3c_pm_show_resume_irqs(IRQ_EINT0, __raw_readl(S3C2410_SRCPND), in s3c_pm_arch_show_resume_irqs()
77 s3c_pm_show_resume_irqs(IRQ_EINT4-4, __raw_readl(S3C2410_EINTPEND), in s3c_pm_arch_show_resume_irqs()
/OK3568_Linux_fs/kernel/arch/mips/pci/
H A Dops-tx4927.c69 __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff) in mkaddr()
80 while (__raw_readl(&pcicptr->pcicstatus) & TX4927_PCIC_PCICSTATUS_IWB) in check_abort()
82 if (__raw_readl(&pcicptr->pcistatus) in check_abort()
84 __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff) in check_abort()
110 return __raw_readl(&pcicptr->g2pcfgdata); in icd_readl()
230 __raw_readl(&pcicptr->pciid) >> 16, in tx4927_pcic_setup()
231 __raw_readl(&pcicptr->pciid) & 0xffff, in tx4927_pcic_setup()
232 __raw_readl(&pcicptr->pciccrev) & 0xff, in tx4927_pcic_setup()
239 __raw_writel(__raw_readl(&pcicptr->pciccfg) in tx4927_pcic_setup()
307 __raw_writel(__raw_readl(&pcicptr->pciccfg) in tx4927_pcic_setup()
[all …]
H A Dpci-ar724x.c60 reset = __raw_readl(apc->ctrl_base + AR724X_PCI_REG_RESET); in ar724x_pci_check_link()
86 data = __raw_readl(base + (where & ~3)); in ar724x_pci_local_write()
108 __raw_readl(base + (where & ~3)); in ar724x_pci_local_write()
128 data = __raw_readl(base + (where & ~3)); in ar724x_pci_read()
197 data = __raw_readl(base + (where & ~3)); in ar724x_pci_write()
219 __raw_readl(base + (where & ~3)); in ar724x_pci_write()
238 pending = __raw_readl(base + AR724X_PCI_REG_INT_STATUS) & in ar724x_pci_irq_handler()
239 __raw_readl(base + AR724X_PCI_REG_INT_MASK); in ar724x_pci_irq_handler()
261 t = __raw_readl(base + AR724X_PCI_REG_INT_MASK); in ar724x_pci_irq_unmask()
265 __raw_readl(base + AR724X_PCI_REG_INT_MASK); in ar724x_pci_irq_unmask()
[all …]
H A Dpci-alchemy.c114 r = __raw_readl(ctx->regs + PCI_REG_STATCMD) & 0x0000ffff; in config_access()
157 *data = __raw_readl(ctx->pci_cfg_vm->addr + offset); in config_access()
164 status = __raw_readl(ctx->regs + PCI_REG_STATCMD); in config_access()
313 ctx->pm[0] = __raw_readl(ctx->regs + PCI_REG_CMEM); in alchemy_pci_suspend()
314 ctx->pm[1] = __raw_readl(ctx->regs + PCI_REG_CONFIG) & 0x0009ffff; in alchemy_pci_suspend()
315 ctx->pm[2] = __raw_readl(ctx->regs + PCI_REG_B2BMASK_CCH); in alchemy_pci_suspend()
316 ctx->pm[3] = __raw_readl(ctx->regs + PCI_REG_B2BBASE0_VID); in alchemy_pci_suspend()
317 ctx->pm[4] = __raw_readl(ctx->regs + PCI_REG_B2BBASE1_SID); in alchemy_pci_suspend()
318 ctx->pm[5] = __raw_readl(ctx->regs + PCI_REG_MWMASK_DEV); in alchemy_pci_suspend()
319 ctx->pm[6] = __raw_readl(ctx->regs + PCI_REG_MWBASE_REV_CCL); in alchemy_pci_suspend()
[all …]
/OK3568_Linux_fs/kernel/arch/arm/mach-pxa/
H A Dsmemc.c22 msc[0] = __raw_readl(MSC0); in pxa3xx_smemc_suspend()
23 msc[1] = __raw_readl(MSC1); in pxa3xx_smemc_suspend()
24 sxcnfg = __raw_readl(SXCNFG); in pxa3xx_smemc_suspend()
25 memclkcfg = __raw_readl(MEMCLKCFG); in pxa3xx_smemc_suspend()
26 csadrcfg[0] = __raw_readl(CSADRCFG0); in pxa3xx_smemc_suspend()
27 csadrcfg[1] = __raw_readl(CSADRCFG1); in pxa3xx_smemc_suspend()
28 csadrcfg[2] = __raw_readl(CSADRCFG2); in pxa3xx_smemc_suspend()
29 csadrcfg[3] = __raw_readl(CSADRCFG3); in pxa3xx_smemc_suspend()
/OK3568_Linux_fs/kernel/arch/arm/mach-mmp/
H A Dpm-mmp2.c47 data |= __raw_readl(MPMU_WUCRM_PJ); in mmp2_set_wake()
52 data = ~data & __raw_readl(MPMU_WUCRM_PJ); in mmp2_set_wake()
68 val = __raw_readl(CIU_REG(0x1c)); in pm_scu_clk_disable()
84 val = __raw_readl(CIU_REG(0x1c)); in pm_scu_clk_enable()
105 val = __raw_readl(MPMU_PLL2_CTRL1); in pm_mpmu_clk_enable()
116 idle_cfg = __raw_readl(APMU_PJ_IDLE_CFG); in mmp2_pm_enter_lowpower_mode()
117 apcr = __raw_readl(MPMU_PCR_PJ); in mmp2_pm_enter_lowpower_mode()
162 temp = __raw_readl(MMP2_ICU_INT4_MASK); in mmp2_pm_enter()
168 temp = __raw_readl(APMU_SRAM_PWR_DWN); in mmp2_pm_enter()
237 __raw_writel(__raw_readl(CIU_REG(0x8)) & ~(0x1 << 23), CIU_REG(0x8)); in mmp2_pm_init()
[all …]
H A Dpm-pxa910.c112 awucrm |= __raw_readl(MPMU_AWUCRM); in pxa910_set_wake()
116 apcr = ~apcr & __raw_readl(MPMU_APCR); in pxa910_set_wake()
121 awucrm = ~awucrm & __raw_readl(MPMU_AWUCRM); in pxa910_set_wake()
125 apcr |= __raw_readl(MPMU_APCR); in pxa910_set_wake()
136 idle_cfg = __raw_readl(APMU_MOH_IDLE_CFG); in pxa910_pm_enter_lowpower_mode()
137 apcr = __raw_readl(MPMU_APCR); in pxa910_pm_enter_lowpower_mode()
192 reg = __raw_readl(ICU_INT_CONF(IRQ_PXA910_PMIC_INT)); in pxa910_pm_enter()
196 idle_cfg = __raw_readl(APMU_MOH_IDLE_CFG); in pxa910_pm_enter()
215 idle_cfg = __raw_readl(APMU_MOH_IDLE_CFG); in pxa910_pm_enter()
262 __raw_writel(__raw_readl(APMU_SQU_CLK_GATE_CTRL) | (1 << 30), in pxa910_pm_init()
[all …]
/OK3568_Linux_fs/u-boot/drivers/video/
H A Dipu_common.c154 reg = __raw_readl(clk->enable_reg); in clk_ipu_enable()
160 reg = __raw_readl(&mxc_ccm->ccdr); in clk_ipu_enable()
165 reg = __raw_readl(&mxc_ccm->clpcr); in clk_ipu_enable()
176 reg = __raw_readl(clk->enable_reg); in clk_ipu_disable()
185 reg = __raw_readl(&mxc_ccm->ccdr); in clk_ipu_disable()
190 reg = __raw_readl(&mxc_ccm->clpcr); in clk_ipu_disable()
275 #define idma_is_set(reg, dma) (__raw_readl(reg(dma)) & idma_mask(dma))
282 div = __raw_readl(DI_BS_CLKGEN0(clk->id)); in ipu_pixel_clk_recalc()
364 u32 disp_gen = __raw_readl(IPU_DISP_GEN); in ipu_pixel_clk_enable()
373 u32 disp_gen = __raw_readl(IPU_DISP_GEN); in ipu_pixel_clk_disable()
[all …]
H A Dipu_disp.c141 u32 dmfc_gen1 = __raw_readl(DMFC_GENERAL1); in ipu_dmfc_set_wait4eot()
195 reg = __raw_readl(DI_DW_GEN(di, wave_gen)); in ipu_di_data_pin_config()
232 reg = __raw_readl(DI_STP_REP(di, wave_gen)); in ipu_di_sync_config()
243 reg = __raw_readl(DC_MAP_CONF_VAL(ptr)); in ipu_dc_map_config()
248 reg = __raw_readl(DC_MAP_CONF_PTR(map)); in ipu_dc_map_config()
256 u32 reg = __raw_readl(DC_MAP_CONF_PTR(map)); in ipu_dc_map_clear()
284 reg = __raw_readl(DC_RL_CH(chan, event)); in ipu_dc_link_event()
387 reg = __raw_readl(DP_COM_CONF()); in ipu_dp_csc_setup()
413 reg = __raw_readl(IPU_SRM_PRI2) | 0x8; in ipu_dp_csc_setup()
469 reg = __raw_readl(DP_COM_CONF()); in ipu_dp_init()
[all …]
/OK3568_Linux_fs/kernel/arch/sh/boards/mach-dreamcast/
H A Drtc.c39 val1 = ((__raw_readl(AICA_RTC_SECS_H) & 0xffff) << 16) | in aica_rtc_gettimeofday()
40 (__raw_readl(AICA_RTC_SECS_L) & 0xffff); in aica_rtc_gettimeofday()
42 val2 = ((__raw_readl(AICA_RTC_SECS_H) & 0xffff) << 16) | in aica_rtc_gettimeofday()
43 (__raw_readl(AICA_RTC_SECS_L) & 0xffff); in aica_rtc_gettimeofday()
71 val1 = ((__raw_readl(AICA_RTC_SECS_H) & 0xffff) << 16) | in aica_rtc_settimeofday()
72 (__raw_readl(AICA_RTC_SECS_L) & 0xffff); in aica_rtc_settimeofday()
74 val2 = ((__raw_readl(AICA_RTC_SECS_H) & 0xffff) << 16) | in aica_rtc_settimeofday()
75 (__raw_readl(AICA_RTC_SECS_L) & 0xffff); in aica_rtc_settimeofday()
/OK3568_Linux_fs/u-boot/drivers/rtc/
H A Dimxdi.c82 if ((__raw_readl(&data.regs->dsr) & DSR_WEF) == 0) in clear_write_error()
109 if ((__raw_readl(&data.regs->dsr) & (DSR_WCF | DSR_WEF)) != 0) { in di_write_wait()
120 if (__raw_readl(&data.regs->dsr) & DSR_WEF) { in di_write_wait()
141 if (__raw_readl(&data.regs->dsr) & DSR_NVF) { in di_init()
156 if (__raw_readl(&data.regs->dsr) & DSR_CAF) { in di_init()
163 if (__raw_readl(&data.regs->dtcmr) == 0) { in di_init()
170 if (!(__raw_readl(&data.regs->dcr) & DCR_TCE)) { in di_init()
171 rc = DI_WRITE_WAIT(__raw_readl(&data.regs->dcr) | DCR_TCE, dcr); in di_init()
194 now = __raw_readl(&data.regs->dtcmr); in rtc_get()
/OK3568_Linux_fs/kernel/arch/mips/ath79/
H A Dclock.c105 pll = __raw_readl(pll_base + AR71XX_PLL_REG_CPU_CONFIG); in ar71xx_clocks_init()
131 pll = __raw_readl(pll_base + AR724X_PLL_REG_CPU_CONFIG); in ar724x_clocks_init()
165 clock_ctrl = __raw_readl(pll_base + AR933X_PLL_CLOCK_CTRL_REG); in ar933x_clocks_init()
178 cpu_config = __raw_readl(pll_base + AR933X_PLL_CPU_CONFIG_REG); in ar933x_clocks_init()
253 pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL2_REG); in ar934x_clocks_init()
257 pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL1_REG); in ar934x_clocks_init()
265 pll = __raw_readl(pll_base + AR934X_PLL_CPU_CONFIG_REG); in ar934x_clocks_init()
280 pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL2_REG); in ar934x_clocks_init()
284 pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL1_REG); in ar934x_clocks_init()
292 pll = __raw_readl(pll_base + AR934X_PLL_DDR_CONFIG_REG); in ar934x_clocks_init()
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-imx/mx6/
H A Dclock.c32 reg = __raw_readl(&imx_ccm->CCGR2); in enable_ocotp_clk()
86 reg = __raw_readl(&imx_ccm->CCGR6); in enable_usboh3_clk()
167 reg = __raw_readl(&imx_ccm->CCGR2); in enable_i2c_clk()
183 reg = __raw_readl(addr); in enable_i2c_clk()
204 reg = __raw_readl(&imx_ccm->CCGR1); in enable_spi_clk()
218 div = __raw_readl(&imx_ccm->analog_pll_sys); in decode_pll()
223 div = __raw_readl(&imx_ccm->analog_pll_528); in decode_pll()
228 div = __raw_readl(&imx_ccm->analog_usb1_pll_480_ctrl); in decode_pll()
233 div = __raw_readl(&imx_ccm->analog_pll_enet); in decode_pll()
238 div = __raw_readl(&imx_ccm->analog_pll_audio); in decode_pll()
[all …]
/OK3568_Linux_fs/kernel/drivers/soc/ixp4xx/
H A Dixp4xx-qmgr.c42 val = __raw_readl(&qmgr_regs->acc[queue][0]); in qmgr_get_entry()
54 return (__raw_readl(&qmgr_regs->stat1[queue >> 3]) in __qmgr_get_stat1()
61 return (__raw_readl(&qmgr_regs->stat2[queue >> 4]) in __qmgr_get_stat2()
86 return (__raw_readl(&qmgr_regs->statne_h) >> in qmgr_stat_below_low_watermark()
100 return (__raw_readl(&qmgr_regs->statf_h) >> in qmgr_stat_full()
128 __raw_writel((__raw_readl(reg) & ~(7 << bit)) | (src << bit), in qmgr_set_irq()
148 en_bitmap = __raw_readl(&qmgr_regs->irqen[0]); in qmgr_irq1_a0()
152 src = __raw_readl(&qmgr_regs->irqsrc[i >> 3]); in qmgr_irq1_a0()
153 stat = __raw_readl(&qmgr_regs->stat1[i >> 3]); in qmgr_irq1_a0()
173 req_bitmap = __raw_readl(&qmgr_regs->irqen[1]) & in qmgr_irq2_a0()
[all …]
/OK3568_Linux_fs/kernel/drivers/edac/
H A Dcpc925_edac.c327 mbmr = __raw_readl(pdata->vbase + REG_MBMR_OFFSET + in cpc925_init_csrows()
329 mbbar = __raw_readl(pdata->vbase + REG_MBBAR_OFFSET + in cpc925_init_csrows()
387 apimask = __raw_readl(pdata->vbase + REG_APIMASK_OFFSET); in cpc925_mc_init()
394 mccr = __raw_readl(pdata->vbase + REG_MCCR_OFFSET); in cpc925_mc_init()
529 apiexcp = __raw_readl(pdata->vbase + REG_APIEXCP_OFFSET); in cpc925_mc_check()
533 mesr = __raw_readl(pdata->vbase + REG_MESR_OFFSET); in cpc925_mc_check()
536 mear = __raw_readl(pdata->vbase + REG_MEAR_OFFSET); in cpc925_mc_check()
560 __raw_readl(pdata->vbase + REG_APIMASK_OFFSET)); in cpc925_mc_check()
564 __raw_readl(pdata->vbase + REG_MSCR_OFFSET)); in cpc925_mc_check()
566 __raw_readl(pdata->vbase + REG_MSRSR_OFFSET)); in cpc925_mc_check()
[all …]
/OK3568_Linux_fs/u-boot/drivers/mtd/nand/raw/
H A Ddavinci_nand.c81 *(u32 *)buf = __raw_readl(nand); in nand_davinci_read_buf()
170 ecc = __raw_readl(&(davinci_emif_regs->nandfecc[ in nand_davinci_readecc()
183 val = __raw_readl(&davinci_emif_regs->nandfcr); in nand_davinci_enable_hwecc()
485 val = __raw_readl(&davinci_emif_regs->nandfcr); in nand_davinci_4bit_enable_hwecc()
493 val = __raw_readl(&davinci_emif_regs->nand4bitecc[0]); in nand_davinci_4bit_enable_hwecc()
505 ecc[i] = __raw_readl(&davinci_emif_regs->nand4bitecc[i]) & in nand_davinci_4bit_readecc()
627 val = __raw_readl(&davinci_emif_regs->nandfsr); in nand_davinci_4bit_correct_data()
643 val = __raw_readl(&davinci_emif_regs->nanderradd1); in nand_davinci_4bit_correct_data()
660 val = __raw_readl(&davinci_emif_regs->nandfsr); in nand_davinci_4bit_correct_data()
671 val = __raw_readl(&davinci_emif_regs->nandfsr); in nand_davinci_4bit_correct_data()
[all …]
/OK3568_Linux_fs/kernel/drivers/soc/samsung/
H A Ds3c-pm-debug.c51 save->ulcon = __raw_readl(regs + S3C2410_ULCON); in s3c_pm_save_uarts()
52 save->ucon = __raw_readl(regs + S3C2410_UCON); in s3c_pm_save_uarts()
53 save->ufcon = __raw_readl(regs + S3C2410_UFCON); in s3c_pm_save_uarts()
54 save->umcon = __raw_readl(regs + S3C2410_UMCON); in s3c_pm_save_uarts()
55 save->ubrdiv = __raw_readl(regs + S3C2410_UBRDIV); in s3c_pm_save_uarts()
58 save->udivslot = __raw_readl(regs + S3C2443_DIVSLOT); in s3c_pm_save_uarts()
/OK3568_Linux_fs/kernel/arch/arm/mach-cns3xxx/
H A Dpm.c17 u32 reg = __raw_readl(PM_CLK_GATE_REG); in cns3xxx_pwr_clk_en()
26 u32 reg = __raw_readl(PM_CLK_GATE_REG); in cns3xxx_pwr_clk_dis()
35 u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG); in cns3xxx_pwr_power_up()
47 u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG); in cns3xxx_pwr_power_down()
57 u32 reg = __raw_readl(PM_SOFT_RST_REG); in cns3xxx_pwr_soft_rst_force()
105 u32 reg = __raw_readl(PM_CLK_CTRL_REG); in cns3xxx_cpu_clock()

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