1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Static Memory Controller
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #include <linux/module.h>
7*4882a593Smuzhiyun #include <linux/kernel.h>
8*4882a593Smuzhiyun #include <linux/init.h>
9*4882a593Smuzhiyun #include <linux/io.h>
10*4882a593Smuzhiyun #include <linux/syscore_ops.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <mach/hardware.h>
13*4882a593Smuzhiyun #include <mach/smemc.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #ifdef CONFIG_PM
16*4882a593Smuzhiyun static unsigned long msc[2];
17*4882a593Smuzhiyun static unsigned long sxcnfg, memclkcfg;
18*4882a593Smuzhiyun static unsigned long csadrcfg[4];
19*4882a593Smuzhiyun
pxa3xx_smemc_suspend(void)20*4882a593Smuzhiyun static int pxa3xx_smemc_suspend(void)
21*4882a593Smuzhiyun {
22*4882a593Smuzhiyun msc[0] = __raw_readl(MSC0);
23*4882a593Smuzhiyun msc[1] = __raw_readl(MSC1);
24*4882a593Smuzhiyun sxcnfg = __raw_readl(SXCNFG);
25*4882a593Smuzhiyun memclkcfg = __raw_readl(MEMCLKCFG);
26*4882a593Smuzhiyun csadrcfg[0] = __raw_readl(CSADRCFG0);
27*4882a593Smuzhiyun csadrcfg[1] = __raw_readl(CSADRCFG1);
28*4882a593Smuzhiyun csadrcfg[2] = __raw_readl(CSADRCFG2);
29*4882a593Smuzhiyun csadrcfg[3] = __raw_readl(CSADRCFG3);
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun return 0;
32*4882a593Smuzhiyun }
33*4882a593Smuzhiyun
pxa3xx_smemc_resume(void)34*4882a593Smuzhiyun static void pxa3xx_smemc_resume(void)
35*4882a593Smuzhiyun {
36*4882a593Smuzhiyun __raw_writel(msc[0], MSC0);
37*4882a593Smuzhiyun __raw_writel(msc[1], MSC1);
38*4882a593Smuzhiyun __raw_writel(sxcnfg, SXCNFG);
39*4882a593Smuzhiyun __raw_writel(memclkcfg, MEMCLKCFG);
40*4882a593Smuzhiyun __raw_writel(csadrcfg[0], CSADRCFG0);
41*4882a593Smuzhiyun __raw_writel(csadrcfg[1], CSADRCFG1);
42*4882a593Smuzhiyun __raw_writel(csadrcfg[2], CSADRCFG2);
43*4882a593Smuzhiyun __raw_writel(csadrcfg[3], CSADRCFG3);
44*4882a593Smuzhiyun /* CSMSADRCFG wakes up in its default state (0), so we need to set it */
45*4882a593Smuzhiyun __raw_writel(0x2, CSMSADRCFG);
46*4882a593Smuzhiyun }
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun static struct syscore_ops smemc_syscore_ops = {
49*4882a593Smuzhiyun .suspend = pxa3xx_smemc_suspend,
50*4882a593Smuzhiyun .resume = pxa3xx_smemc_resume,
51*4882a593Smuzhiyun };
52*4882a593Smuzhiyun
smemc_init(void)53*4882a593Smuzhiyun static int __init smemc_init(void)
54*4882a593Smuzhiyun {
55*4882a593Smuzhiyun if (cpu_is_pxa3xx()) {
56*4882a593Smuzhiyun /*
57*4882a593Smuzhiyun * The only documentation we have on the
58*4882a593Smuzhiyun * Chip Select Configuration Register (CSMSADRCFG) is that
59*4882a593Smuzhiyun * it must be programmed to 0x2.
60*4882a593Smuzhiyun * Moreover, in the bit definitions, the second bit
61*4882a593Smuzhiyun * (CSMSADRCFG[1]) is called "SETALWAYS".
62*4882a593Smuzhiyun * Other bits are reserved in this register.
63*4882a593Smuzhiyun */
64*4882a593Smuzhiyun __raw_writel(0x2, CSMSADRCFG);
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun register_syscore_ops(&smemc_syscore_ops);
67*4882a593Smuzhiyun }
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun return 0;
70*4882a593Smuzhiyun }
71*4882a593Smuzhiyun subsys_initcall(smemc_init);
72*4882a593Smuzhiyun #endif
73