Lines Matching refs:__raw_readl
29 while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) in ddr3_init_ddrphy()
35 tmp = __raw_readl(base + KS2_DDRPHY_PGCR1_OFFSET); in ddr3_init_ddrphy()
45 tmp = __raw_readl(base + KS2_DDRPHY_DCR_OFFSET); in ddr3_init_ddrphy()
64 while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1) in ddr3_init_ddrphy()
98 while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1) in ddr3_init_ddrphy()
115 u32 value = __raw_readl(base + KS2_DDR3_MIDR_OFFSET); in ddr3_ecc_support_rmw()
134 data = __raw_readl(base + KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET); in ddr3_ecc_config()
332 u32 value = __raw_readl(base + KS2_DDR3_ECC_INT_STATUS_OFFSET); in ddr3_check_ecc_int()
350 value = __raw_readl(base + KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET); in ddr3_check_ecc_int()
353 value = __raw_readl(base + in ddr3_check_ecc_int()
393 tmp_a = __raw_readl(KS2_DDR3A_DDRPHYC + KS2_DDRPHY_PGSR0_OFFSET); in ddr3_err_reset_workaround()
394 tmp_b = __raw_readl(KS2_DDR3B_DDRPHYC + KS2_DDRPHY_PGSR0_OFFSET); in ddr3_err_reset_workaround()
412 tmp_a = __raw_readl(KS2_PSC_BASE + in ddr3_err_reset_workaround()
423 tmp_b = __raw_readl(KS2_PSC_BASE + in ddr3_err_reset_workaround()
433 tmp = __raw_readl(KS2_RSTCTRL); in ddr3_err_reset_workaround()
442 tmp = __raw_readl(KS2_RSTCTRL_RSCFG); in ddr3_err_reset_workaround()