1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright 2008 Cavium Networks
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #include <linux/init.h>
7*4882a593Smuzhiyun #include <linux/module.h>
8*4882a593Smuzhiyun #include <linux/io.h>
9*4882a593Smuzhiyun #include <linux/delay.h>
10*4882a593Smuzhiyun #include <linux/atomic.h>
11*4882a593Smuzhiyun #include "cns3xxx.h"
12*4882a593Smuzhiyun #include "pm.h"
13*4882a593Smuzhiyun #include "core.h"
14*4882a593Smuzhiyun
cns3xxx_pwr_clk_en(unsigned int block)15*4882a593Smuzhiyun void cns3xxx_pwr_clk_en(unsigned int block)
16*4882a593Smuzhiyun {
17*4882a593Smuzhiyun u32 reg = __raw_readl(PM_CLK_GATE_REG);
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun reg |= (block & PM_CLK_GATE_REG_MASK);
20*4882a593Smuzhiyun __raw_writel(reg, PM_CLK_GATE_REG);
21*4882a593Smuzhiyun }
22*4882a593Smuzhiyun EXPORT_SYMBOL(cns3xxx_pwr_clk_en);
23*4882a593Smuzhiyun
cns3xxx_pwr_clk_dis(unsigned int block)24*4882a593Smuzhiyun void cns3xxx_pwr_clk_dis(unsigned int block)
25*4882a593Smuzhiyun {
26*4882a593Smuzhiyun u32 reg = __raw_readl(PM_CLK_GATE_REG);
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun reg &= ~(block & PM_CLK_GATE_REG_MASK);
29*4882a593Smuzhiyun __raw_writel(reg, PM_CLK_GATE_REG);
30*4882a593Smuzhiyun }
31*4882a593Smuzhiyun EXPORT_SYMBOL(cns3xxx_pwr_clk_dis);
32*4882a593Smuzhiyun
cns3xxx_pwr_power_up(unsigned int block)33*4882a593Smuzhiyun void cns3xxx_pwr_power_up(unsigned int block)
34*4882a593Smuzhiyun {
35*4882a593Smuzhiyun u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG);
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun reg &= ~(block & CNS3XXX_PWR_PLL_ALL);
38*4882a593Smuzhiyun __raw_writel(reg, PM_PLL_HM_PD_CTRL_REG);
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun /* Wait for 300us for the PLL output clock locked. */
41*4882a593Smuzhiyun udelay(300);
42*4882a593Smuzhiyun };
43*4882a593Smuzhiyun EXPORT_SYMBOL(cns3xxx_pwr_power_up);
44*4882a593Smuzhiyun
cns3xxx_pwr_power_down(unsigned int block)45*4882a593Smuzhiyun void cns3xxx_pwr_power_down(unsigned int block)
46*4882a593Smuzhiyun {
47*4882a593Smuzhiyun u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG);
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun /* write '1' to power down */
50*4882a593Smuzhiyun reg |= (block & CNS3XXX_PWR_PLL_ALL);
51*4882a593Smuzhiyun __raw_writel(reg, PM_PLL_HM_PD_CTRL_REG);
52*4882a593Smuzhiyun };
53*4882a593Smuzhiyun EXPORT_SYMBOL(cns3xxx_pwr_power_down);
54*4882a593Smuzhiyun
cns3xxx_pwr_soft_rst_force(unsigned int block)55*4882a593Smuzhiyun static void cns3xxx_pwr_soft_rst_force(unsigned int block)
56*4882a593Smuzhiyun {
57*4882a593Smuzhiyun u32 reg = __raw_readl(PM_SOFT_RST_REG);
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun /*
60*4882a593Smuzhiyun * bit 0, 28, 29 => program low to reset,
61*4882a593Smuzhiyun * the other else program low and then high
62*4882a593Smuzhiyun */
63*4882a593Smuzhiyun if (block & 0x30000001) {
64*4882a593Smuzhiyun reg &= ~(block & PM_SOFT_RST_REG_MASK);
65*4882a593Smuzhiyun } else {
66*4882a593Smuzhiyun reg &= ~(block & PM_SOFT_RST_REG_MASK);
67*4882a593Smuzhiyun __raw_writel(reg, PM_SOFT_RST_REG);
68*4882a593Smuzhiyun reg |= (block & PM_SOFT_RST_REG_MASK);
69*4882a593Smuzhiyun }
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun __raw_writel(reg, PM_SOFT_RST_REG);
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun
cns3xxx_pwr_soft_rst(unsigned int block)74*4882a593Smuzhiyun void cns3xxx_pwr_soft_rst(unsigned int block)
75*4882a593Smuzhiyun {
76*4882a593Smuzhiyun static unsigned int soft_reset;
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun if (soft_reset & block) {
79*4882a593Smuzhiyun /* SPI/I2C/GPIO use the same block, reset once. */
80*4882a593Smuzhiyun return;
81*4882a593Smuzhiyun } else {
82*4882a593Smuzhiyun soft_reset |= block;
83*4882a593Smuzhiyun }
84*4882a593Smuzhiyun cns3xxx_pwr_soft_rst_force(block);
85*4882a593Smuzhiyun }
86*4882a593Smuzhiyun EXPORT_SYMBOL(cns3xxx_pwr_soft_rst);
87*4882a593Smuzhiyun
cns3xxx_restart(enum reboot_mode mode,const char * cmd)88*4882a593Smuzhiyun void cns3xxx_restart(enum reboot_mode mode, const char *cmd)
89*4882a593Smuzhiyun {
90*4882a593Smuzhiyun /*
91*4882a593Smuzhiyun * To reset, we hit the on-board reset register
92*4882a593Smuzhiyun * in the system FPGA.
93*4882a593Smuzhiyun */
94*4882a593Smuzhiyun cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(GLOBAL));
95*4882a593Smuzhiyun }
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun /*
98*4882a593Smuzhiyun * cns3xxx_cpu_clock - return CPU/L2 clock
99*4882a593Smuzhiyun * aclk: cpu clock/2
100*4882a593Smuzhiyun * hclk: cpu clock/4
101*4882a593Smuzhiyun * pclk: cpu clock/8
102*4882a593Smuzhiyun */
cns3xxx_cpu_clock(void)103*4882a593Smuzhiyun int cns3xxx_cpu_clock(void)
104*4882a593Smuzhiyun {
105*4882a593Smuzhiyun u32 reg = __raw_readl(PM_CLK_CTRL_REG);
106*4882a593Smuzhiyun int cpu;
107*4882a593Smuzhiyun int cpu_sel;
108*4882a593Smuzhiyun int div_sel;
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun cpu_sel = (reg >> PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL) & 0xf;
111*4882a593Smuzhiyun div_sel = (reg >> PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV) & 0x3;
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun cpu = (300 + ((cpu_sel / 3) * 100) + ((cpu_sel % 3) * 33)) >> div_sel;
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun return cpu;
116*4882a593Smuzhiyun }
117*4882a593Smuzhiyun EXPORT_SYMBOL(cns3xxx_cpu_clock);
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun atomic_t usb_pwr_ref = ATOMIC_INIT(0);
120*4882a593Smuzhiyun EXPORT_SYMBOL(usb_pwr_ref);
121