1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright 2008 Simtec Electronics
4*4882a593Smuzhiyun * Ben Dooks <ben@simtec.co.uk>
5*4882a593Smuzhiyun * http://armlinux.simtec.co.uk/
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * S3C24xx - PM core support for arch/arm/plat-s3c/pm.c
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/delay.h>
11*4882a593Smuzhiyun #include <linux/io.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include "regs-clock.h"
14*4882a593Smuzhiyun #include "regs-irq-s3c24xx.h"
15*4882a593Smuzhiyun #include <mach/irqs.h>
16*4882a593Smuzhiyun
s3c_pm_debug_init_uart(void)17*4882a593Smuzhiyun static inline void s3c_pm_debug_init_uart(void)
18*4882a593Smuzhiyun {
19*4882a593Smuzhiyun #ifdef CONFIG_SAMSUNG_PM_DEBUG
20*4882a593Smuzhiyun unsigned long tmp = __raw_readl(S3C2410_CLKCON);
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun /* re-start uart clocks */
23*4882a593Smuzhiyun tmp |= S3C2410_CLKCON_UART0;
24*4882a593Smuzhiyun tmp |= S3C2410_CLKCON_UART1;
25*4882a593Smuzhiyun tmp |= S3C2410_CLKCON_UART2;
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun __raw_writel(tmp, S3C2410_CLKCON);
28*4882a593Smuzhiyun udelay(10);
29*4882a593Smuzhiyun #endif
30*4882a593Smuzhiyun }
31*4882a593Smuzhiyun
s3c_pm_arch_prepare_irqs(void)32*4882a593Smuzhiyun static inline void s3c_pm_arch_prepare_irqs(void)
33*4882a593Smuzhiyun {
34*4882a593Smuzhiyun __raw_writel(s3c_irqwake_intmask, S3C2410_INTMSK);
35*4882a593Smuzhiyun __raw_writel(s3c_irqwake_eintmask, S3C2410_EINTMASK);
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun /* ack any outstanding external interrupts before we go to sleep */
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun __raw_writel(__raw_readl(S3C2410_EINTPEND), S3C2410_EINTPEND);
40*4882a593Smuzhiyun __raw_writel(__raw_readl(S3C2410_INTPND), S3C2410_INTPND);
41*4882a593Smuzhiyun __raw_writel(__raw_readl(S3C2410_SRCPND), S3C2410_SRCPND);
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun }
44*4882a593Smuzhiyun
s3c_pm_arch_stop_clocks(void)45*4882a593Smuzhiyun static inline void s3c_pm_arch_stop_clocks(void)
46*4882a593Smuzhiyun {
47*4882a593Smuzhiyun __raw_writel(0x00, S3C2410_CLKCON); /* turn off clocks over sleep */
48*4882a593Smuzhiyun }
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun /* s3c2410_pm_show_resume_irqs
51*4882a593Smuzhiyun *
52*4882a593Smuzhiyun * print any IRQs asserted at resume time (ie, we woke from)
53*4882a593Smuzhiyun */
s3c_pm_show_resume_irqs(int start,unsigned long which,unsigned long mask)54*4882a593Smuzhiyun static inline void s3c_pm_show_resume_irqs(int start, unsigned long which,
55*4882a593Smuzhiyun unsigned long mask)
56*4882a593Smuzhiyun {
57*4882a593Smuzhiyun int i;
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun which &= ~mask;
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun for (i = 0; i <= 31; i++) {
62*4882a593Smuzhiyun if (which & (1L<<i)) {
63*4882a593Smuzhiyun S3C_PMDBG("IRQ %d asserted at resume\n", start+i);
64*4882a593Smuzhiyun }
65*4882a593Smuzhiyun }
66*4882a593Smuzhiyun }
67*4882a593Smuzhiyun
s3c_pm_arch_show_resume_irqs(void)68*4882a593Smuzhiyun static inline void s3c_pm_arch_show_resume_irqs(void)
69*4882a593Smuzhiyun {
70*4882a593Smuzhiyun S3C_PMDBG("post sleep: IRQs 0x%08x, 0x%08x\n",
71*4882a593Smuzhiyun __raw_readl(S3C2410_SRCPND),
72*4882a593Smuzhiyun __raw_readl(S3C2410_EINTPEND));
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun s3c_pm_show_resume_irqs(IRQ_EINT0, __raw_readl(S3C2410_SRCPND),
75*4882a593Smuzhiyun s3c_irqwake_intmask);
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun s3c_pm_show_resume_irqs(IRQ_EINT4-4, __raw_readl(S3C2410_EINTPEND),
78*4882a593Smuzhiyun s3c_irqwake_eintmask);
79*4882a593Smuzhiyun }
80*4882a593Smuzhiyun
s3c_pm_restored_gpios(void)81*4882a593Smuzhiyun static inline void s3c_pm_restored_gpios(void) { }
samsung_pm_saved_gpios(void)82*4882a593Smuzhiyun static inline void samsung_pm_saved_gpios(void) { }
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun /* state for IRQs over sleep */
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun /* default is to allow for EINT0..EINT15, and IRQ_RTC as wakeup sources
87*4882a593Smuzhiyun *
88*4882a593Smuzhiyun * set bit to 1 in allow bitfield to enable the wakeup settings on it
89*4882a593Smuzhiyun */
90*4882a593Smuzhiyun #ifdef CONFIG_PM_SLEEP
91*4882a593Smuzhiyun #define s3c_irqwake_intallow (1L << 30 | 0xfL)
92*4882a593Smuzhiyun #define s3c_irqwake_eintallow (0x0000fff0L)
93*4882a593Smuzhiyun #else
94*4882a593Smuzhiyun #define s3c_irqwake_eintallow 0
95*4882a593Smuzhiyun #define s3c_irqwake_intallow 0
96*4882a593Smuzhiyun #endif
97