1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun //
3*4882a593Smuzhiyun // Copyright (C) 2013 Samsung Electronics Co., Ltd.
4*4882a593Smuzhiyun // Tomasz Figa <t.figa@samsung.com>
5*4882a593Smuzhiyun // Copyright (C) 2008 Openmoko, Inc.
6*4882a593Smuzhiyun // Copyright (C) 2004-2008 Simtec Electronics
7*4882a593Smuzhiyun // Ben Dooks <ben@simtec.co.uk>
8*4882a593Smuzhiyun // http://armlinux.simtec.co.uk/
9*4882a593Smuzhiyun //
10*4882a593Smuzhiyun // Samsung common power management (suspend to RAM) debug support
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <linux/serial_core.h>
13*4882a593Smuzhiyun #include <linux/serial_s3c.h>
14*4882a593Smuzhiyun #include <linux/io.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #include <asm/mach/map.h>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #include <linux/soc/samsung/s3c-pm.h>
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun static struct pm_uart_save uart_save;
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun extern void printascii(const char *);
23*4882a593Smuzhiyun
s3c_pm_dbg(const char * fmt,...)24*4882a593Smuzhiyun void s3c_pm_dbg(const char *fmt, ...)
25*4882a593Smuzhiyun {
26*4882a593Smuzhiyun va_list va;
27*4882a593Smuzhiyun char buff[256];
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun va_start(va, fmt);
30*4882a593Smuzhiyun vsnprintf(buff, sizeof(buff), fmt, va);
31*4882a593Smuzhiyun va_end(va);
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun printascii(buff);
34*4882a593Smuzhiyun }
35*4882a593Smuzhiyun
s3c_pm_uart_base(void)36*4882a593Smuzhiyun static inline void __iomem *s3c_pm_uart_base(void)
37*4882a593Smuzhiyun {
38*4882a593Smuzhiyun unsigned long paddr;
39*4882a593Smuzhiyun unsigned long vaddr;
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun debug_ll_addr(&paddr, &vaddr);
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun return (void __iomem *)vaddr;
44*4882a593Smuzhiyun }
45*4882a593Smuzhiyun
s3c_pm_save_uarts(bool is_s3c2410)46*4882a593Smuzhiyun void s3c_pm_save_uarts(bool is_s3c2410)
47*4882a593Smuzhiyun {
48*4882a593Smuzhiyun void __iomem *regs = s3c_pm_uart_base();
49*4882a593Smuzhiyun struct pm_uart_save *save = &uart_save;
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun save->ulcon = __raw_readl(regs + S3C2410_ULCON);
52*4882a593Smuzhiyun save->ucon = __raw_readl(regs + S3C2410_UCON);
53*4882a593Smuzhiyun save->ufcon = __raw_readl(regs + S3C2410_UFCON);
54*4882a593Smuzhiyun save->umcon = __raw_readl(regs + S3C2410_UMCON);
55*4882a593Smuzhiyun save->ubrdiv = __raw_readl(regs + S3C2410_UBRDIV);
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun if (!is_s3c2410)
58*4882a593Smuzhiyun save->udivslot = __raw_readl(regs + S3C2443_DIVSLOT);
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun S3C_PMDBG("UART[%p]: ULCON=%04x, UCON=%04x, UFCON=%04x, UBRDIV=%04x\n",
61*4882a593Smuzhiyun regs, save->ulcon, save->ucon, save->ufcon, save->ubrdiv);
62*4882a593Smuzhiyun }
63*4882a593Smuzhiyun
s3c_pm_restore_uarts(bool is_s3c2410)64*4882a593Smuzhiyun void s3c_pm_restore_uarts(bool is_s3c2410)
65*4882a593Smuzhiyun {
66*4882a593Smuzhiyun void __iomem *regs = s3c_pm_uart_base();
67*4882a593Smuzhiyun struct pm_uart_save *save = &uart_save;
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun s3c_pm_arch_update_uart(regs, save);
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun __raw_writel(save->ulcon, regs + S3C2410_ULCON);
72*4882a593Smuzhiyun __raw_writel(save->ucon, regs + S3C2410_UCON);
73*4882a593Smuzhiyun __raw_writel(save->ufcon, regs + S3C2410_UFCON);
74*4882a593Smuzhiyun __raw_writel(save->umcon, regs + S3C2410_UMCON);
75*4882a593Smuzhiyun __raw_writel(save->ubrdiv, regs + S3C2410_UBRDIV);
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun if (!is_s3c2410)
78*4882a593Smuzhiyun __raw_writel(save->udivslot, regs + S3C2443_DIVSLOT);
79*4882a593Smuzhiyun }
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