| /OK3568_Linux_fs/kernel/include/dt-bindings/clock/ |
| H A D | exynos7-clk.h | 88 #define SCLK_PWM 11 macro
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| H A D | s5pv210.h | 191 #define SCLK_PWM 169 macro
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| H A D | rv1108-cru.h | 71 #define SCLK_PWM 121 macro
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| H A D | rk3328-cru.h | 49 #define SCLK_PWM 60 macro
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| /OK3568_Linux_fs/u-boot/include/dt-bindings/clock/ |
| H A D | exynos7420-clk.h | 91 #define SCLK_PWM 11 macro
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| H A D | rv1108-cru.h | 71 #define SCLK_PWM 121 macro
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| H A D | rk3308-cru.h | 39 #define SCLK_PWM 26 macro
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| H A D | rk3328-cru.h | 49 #define SCLK_PWM 60 macro
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| /OK3568_Linux_fs/kernel/arch/arm/boot/dts/ |
| H A D | rv1108.dtsi | 218 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
230 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
242 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
254 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
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| /OK3568_Linux_fs/u-boot/arch/arm/dts/ |
| H A D | rk3308.dtsi | 303 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
314 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
325 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
336 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
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| H A D | rv1108.dtsi | 236 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
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| /OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/ |
| H A D | rk3328.dtsi | 469 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
480 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
491 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
503 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
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| /OK3568_Linux_fs/u-boot/drivers/clk/rockchip/ |
| H A D | clk_rk3308.c | 977 case SCLK_PWM: in rk3308_clk_get_rate()
1062 case SCLK_PWM: in rk3308_clk_set_rate()
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| H A D | clk_rk3328.c | 839 case SCLK_PWM: in rk3328_clk_get_rate()
929 case SCLK_PWM: in rk3328_clk_set_rate()
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| /OK3568_Linux_fs/kernel/drivers/clk/samsung/ |
| H A D | clk-s5pv210.c | 592 GATE(SCLK_PWM, "sclk_pwm", "dout_pwm", CLK_SRC_MASK0, 19,
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| H A D | clk-exynos7.c | 675 GATE(SCLK_PWM, "sclk_pwm", "fin_pll", ENABLE_SCLK_PERIC0, 21, 0, 0),
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| /OK3568_Linux_fs/kernel/drivers/clk/rockchip/ |
| H A D | clk-rv1108.c | 628 COMPOSITE(SCLK_PWM, "clk_pwm", mux_pll_src_2plls_p, 0,
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| H A D | clk-rk3328.c | 467 COMPOSITE(SCLK_PWM, "clk_pwm", mux_2plls_p, 0,
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