1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2013 Samsung Electronics Co., Ltd. 4*4882a593Smuzhiyun * Author: Mateusz Krawczuk <m.krawczuk@partner.samsung.com> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Device Tree binding constants for Samsung S5PV210 clock controller. 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef _DT_BINDINGS_CLOCK_S5PV210_H 10*4882a593Smuzhiyun #define _DT_BINDINGS_CLOCK_S5PV210_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* Core clocks. */ 13*4882a593Smuzhiyun #define FIN_PLL 1 14*4882a593Smuzhiyun #define FOUT_APLL 2 15*4882a593Smuzhiyun #define FOUT_MPLL 3 16*4882a593Smuzhiyun #define FOUT_EPLL 4 17*4882a593Smuzhiyun #define FOUT_VPLL 5 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* Muxes. */ 20*4882a593Smuzhiyun #define MOUT_FLASH 6 21*4882a593Smuzhiyun #define MOUT_PSYS 7 22*4882a593Smuzhiyun #define MOUT_DSYS 8 23*4882a593Smuzhiyun #define MOUT_MSYS 9 24*4882a593Smuzhiyun #define MOUT_VPLL 10 25*4882a593Smuzhiyun #define MOUT_EPLL 11 26*4882a593Smuzhiyun #define MOUT_MPLL 12 27*4882a593Smuzhiyun #define MOUT_APLL 13 28*4882a593Smuzhiyun #define MOUT_VPLLSRC 14 29*4882a593Smuzhiyun #define MOUT_CSIS 15 30*4882a593Smuzhiyun #define MOUT_FIMD 16 31*4882a593Smuzhiyun #define MOUT_CAM1 17 32*4882a593Smuzhiyun #define MOUT_CAM0 18 33*4882a593Smuzhiyun #define MOUT_DAC 19 34*4882a593Smuzhiyun #define MOUT_MIXER 20 35*4882a593Smuzhiyun #define MOUT_HDMI 21 36*4882a593Smuzhiyun #define MOUT_G2D 22 37*4882a593Smuzhiyun #define MOUT_MFC 23 38*4882a593Smuzhiyun #define MOUT_G3D 24 39*4882a593Smuzhiyun #define MOUT_FIMC2 25 40*4882a593Smuzhiyun #define MOUT_FIMC1 26 41*4882a593Smuzhiyun #define MOUT_FIMC0 27 42*4882a593Smuzhiyun #define MOUT_UART3 28 43*4882a593Smuzhiyun #define MOUT_UART2 29 44*4882a593Smuzhiyun #define MOUT_UART1 30 45*4882a593Smuzhiyun #define MOUT_UART0 31 46*4882a593Smuzhiyun #define MOUT_MMC3 32 47*4882a593Smuzhiyun #define MOUT_MMC2 33 48*4882a593Smuzhiyun #define MOUT_MMC1 34 49*4882a593Smuzhiyun #define MOUT_MMC0 35 50*4882a593Smuzhiyun #define MOUT_PWM 36 51*4882a593Smuzhiyun #define MOUT_SPI0 37 52*4882a593Smuzhiyun #define MOUT_SPI1 38 53*4882a593Smuzhiyun #define MOUT_DMC0 39 54*4882a593Smuzhiyun #define MOUT_PWI 40 55*4882a593Smuzhiyun #define MOUT_HPM 41 56*4882a593Smuzhiyun #define MOUT_SPDIF 42 57*4882a593Smuzhiyun #define MOUT_AUDIO2 43 58*4882a593Smuzhiyun #define MOUT_AUDIO1 44 59*4882a593Smuzhiyun #define MOUT_AUDIO0 45 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun /* Dividers. */ 62*4882a593Smuzhiyun #define DOUT_PCLKP 46 63*4882a593Smuzhiyun #define DOUT_HCLKP 47 64*4882a593Smuzhiyun #define DOUT_PCLKD 48 65*4882a593Smuzhiyun #define DOUT_HCLKD 49 66*4882a593Smuzhiyun #define DOUT_PCLKM 50 67*4882a593Smuzhiyun #define DOUT_HCLKM 51 68*4882a593Smuzhiyun #define DOUT_A2M 52 69*4882a593Smuzhiyun #define DOUT_APLL 53 70*4882a593Smuzhiyun #define DOUT_CSIS 54 71*4882a593Smuzhiyun #define DOUT_FIMD 55 72*4882a593Smuzhiyun #define DOUT_CAM1 56 73*4882a593Smuzhiyun #define DOUT_CAM0 57 74*4882a593Smuzhiyun #define DOUT_TBLK 58 75*4882a593Smuzhiyun #define DOUT_G2D 59 76*4882a593Smuzhiyun #define DOUT_MFC 60 77*4882a593Smuzhiyun #define DOUT_G3D 61 78*4882a593Smuzhiyun #define DOUT_FIMC2 62 79*4882a593Smuzhiyun #define DOUT_FIMC1 63 80*4882a593Smuzhiyun #define DOUT_FIMC0 64 81*4882a593Smuzhiyun #define DOUT_UART3 65 82*4882a593Smuzhiyun #define DOUT_UART2 66 83*4882a593Smuzhiyun #define DOUT_UART1 67 84*4882a593Smuzhiyun #define DOUT_UART0 68 85*4882a593Smuzhiyun #define DOUT_MMC3 69 86*4882a593Smuzhiyun #define DOUT_MMC2 70 87*4882a593Smuzhiyun #define DOUT_MMC1 71 88*4882a593Smuzhiyun #define DOUT_MMC0 72 89*4882a593Smuzhiyun #define DOUT_PWM 73 90*4882a593Smuzhiyun #define DOUT_SPI1 74 91*4882a593Smuzhiyun #define DOUT_SPI0 75 92*4882a593Smuzhiyun #define DOUT_DMC0 76 93*4882a593Smuzhiyun #define DOUT_PWI 77 94*4882a593Smuzhiyun #define DOUT_HPM 78 95*4882a593Smuzhiyun #define DOUT_COPY 79 96*4882a593Smuzhiyun #define DOUT_FLASH 80 97*4882a593Smuzhiyun #define DOUT_AUDIO2 81 98*4882a593Smuzhiyun #define DOUT_AUDIO1 82 99*4882a593Smuzhiyun #define DOUT_AUDIO0 83 100*4882a593Smuzhiyun #define DOUT_DPM 84 101*4882a593Smuzhiyun #define DOUT_DVSEM 85 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun /* Gates */ 104*4882a593Smuzhiyun #define SCLK_FIMC 86 105*4882a593Smuzhiyun #define CLK_CSIS 87 106*4882a593Smuzhiyun #define CLK_ROTATOR 88 107*4882a593Smuzhiyun #define CLK_FIMC2 89 108*4882a593Smuzhiyun #define CLK_FIMC1 90 109*4882a593Smuzhiyun #define CLK_FIMC0 91 110*4882a593Smuzhiyun #define CLK_MFC 92 111*4882a593Smuzhiyun #define CLK_G2D 93 112*4882a593Smuzhiyun #define CLK_G3D 94 113*4882a593Smuzhiyun #define CLK_IMEM 95 114*4882a593Smuzhiyun #define CLK_PDMA1 96 115*4882a593Smuzhiyun #define CLK_PDMA0 97 116*4882a593Smuzhiyun #define CLK_MDMA 98 117*4882a593Smuzhiyun #define CLK_DMC1 99 118*4882a593Smuzhiyun #define CLK_DMC0 100 119*4882a593Smuzhiyun #define CLK_NFCON 101 120*4882a593Smuzhiyun #define CLK_SROMC 102 121*4882a593Smuzhiyun #define CLK_CFCON 103 122*4882a593Smuzhiyun #define CLK_NANDXL 104 123*4882a593Smuzhiyun #define CLK_USB_HOST 105 124*4882a593Smuzhiyun #define CLK_USB_OTG 106 125*4882a593Smuzhiyun #define CLK_HDMI 107 126*4882a593Smuzhiyun #define CLK_TVENC 108 127*4882a593Smuzhiyun #define CLK_MIXER 109 128*4882a593Smuzhiyun #define CLK_VP 110 129*4882a593Smuzhiyun #define CLK_DSIM 111 130*4882a593Smuzhiyun #define CLK_FIMD 112 131*4882a593Smuzhiyun #define CLK_TZIC3 113 132*4882a593Smuzhiyun #define CLK_TZIC2 114 133*4882a593Smuzhiyun #define CLK_TZIC1 115 134*4882a593Smuzhiyun #define CLK_TZIC0 116 135*4882a593Smuzhiyun #define CLK_VIC3 117 136*4882a593Smuzhiyun #define CLK_VIC2 118 137*4882a593Smuzhiyun #define CLK_VIC1 119 138*4882a593Smuzhiyun #define CLK_VIC0 120 139*4882a593Smuzhiyun #define CLK_TSI 121 140*4882a593Smuzhiyun #define CLK_HSMMC3 122 141*4882a593Smuzhiyun #define CLK_HSMMC2 123 142*4882a593Smuzhiyun #define CLK_HSMMC1 124 143*4882a593Smuzhiyun #define CLK_HSMMC0 125 144*4882a593Smuzhiyun #define CLK_JTAG 126 145*4882a593Smuzhiyun #define CLK_MODEMIF 127 146*4882a593Smuzhiyun #define CLK_CORESIGHT 128 147*4882a593Smuzhiyun #define CLK_SDM 129 148*4882a593Smuzhiyun #define CLK_SECSS 130 149*4882a593Smuzhiyun #define CLK_PCM2 131 150*4882a593Smuzhiyun #define CLK_PCM1 132 151*4882a593Smuzhiyun #define CLK_PCM0 133 152*4882a593Smuzhiyun #define CLK_SYSCON 134 153*4882a593Smuzhiyun #define CLK_GPIO 135 154*4882a593Smuzhiyun #define CLK_TSADC 136 155*4882a593Smuzhiyun #define CLK_PWM 137 156*4882a593Smuzhiyun #define CLK_WDT 138 157*4882a593Smuzhiyun #define CLK_KEYIF 139 158*4882a593Smuzhiyun #define CLK_UART3 140 159*4882a593Smuzhiyun #define CLK_UART2 141 160*4882a593Smuzhiyun #define CLK_UART1 142 161*4882a593Smuzhiyun #define CLK_UART0 143 162*4882a593Smuzhiyun #define CLK_SYSTIMER 144 163*4882a593Smuzhiyun #define CLK_RTC 145 164*4882a593Smuzhiyun #define CLK_SPI1 146 165*4882a593Smuzhiyun #define CLK_SPI0 147 166*4882a593Smuzhiyun #define CLK_I2C_HDMI_PHY 148 167*4882a593Smuzhiyun #define CLK_I2C1 149 168*4882a593Smuzhiyun #define CLK_I2C2 150 169*4882a593Smuzhiyun #define CLK_I2C0 151 170*4882a593Smuzhiyun #define CLK_I2S1 152 171*4882a593Smuzhiyun #define CLK_I2S2 153 172*4882a593Smuzhiyun #define CLK_I2S0 154 173*4882a593Smuzhiyun #define CLK_AC97 155 174*4882a593Smuzhiyun #define CLK_SPDIF 156 175*4882a593Smuzhiyun #define CLK_TZPC3 157 176*4882a593Smuzhiyun #define CLK_TZPC2 158 177*4882a593Smuzhiyun #define CLK_TZPC1 159 178*4882a593Smuzhiyun #define CLK_TZPC0 160 179*4882a593Smuzhiyun #define CLK_SECKEY 161 180*4882a593Smuzhiyun #define CLK_IEM_APC 162 181*4882a593Smuzhiyun #define CLK_IEM_IEC 163 182*4882a593Smuzhiyun #define CLK_CHIPID 164 183*4882a593Smuzhiyun #define CLK_JPEG 163 184*4882a593Smuzhiyun 185*4882a593Smuzhiyun /* Special clocks*/ 186*4882a593Smuzhiyun #define SCLK_PWI 164 187*4882a593Smuzhiyun #define SCLK_SPDIF 165 188*4882a593Smuzhiyun #define SCLK_AUDIO2 166 189*4882a593Smuzhiyun #define SCLK_AUDIO1 167 190*4882a593Smuzhiyun #define SCLK_AUDIO0 168 191*4882a593Smuzhiyun #define SCLK_PWM 169 192*4882a593Smuzhiyun #define SCLK_SPI1 170 193*4882a593Smuzhiyun #define SCLK_SPI0 171 194*4882a593Smuzhiyun #define SCLK_UART3 172 195*4882a593Smuzhiyun #define SCLK_UART2 173 196*4882a593Smuzhiyun #define SCLK_UART1 174 197*4882a593Smuzhiyun #define SCLK_UART0 175 198*4882a593Smuzhiyun #define SCLK_MMC3 176 199*4882a593Smuzhiyun #define SCLK_MMC2 177 200*4882a593Smuzhiyun #define SCLK_MMC1 178 201*4882a593Smuzhiyun #define SCLK_MMC0 179 202*4882a593Smuzhiyun #define SCLK_FINVPLL 180 203*4882a593Smuzhiyun #define SCLK_CSIS 181 204*4882a593Smuzhiyun #define SCLK_FIMD 182 205*4882a593Smuzhiyun #define SCLK_CAM1 183 206*4882a593Smuzhiyun #define SCLK_CAM0 184 207*4882a593Smuzhiyun #define SCLK_DAC 185 208*4882a593Smuzhiyun #define SCLK_MIXER 186 209*4882a593Smuzhiyun #define SCLK_HDMI 187 210*4882a593Smuzhiyun #define SCLK_FIMC2 188 211*4882a593Smuzhiyun #define SCLK_FIMC1 189 212*4882a593Smuzhiyun #define SCLK_FIMC0 190 213*4882a593Smuzhiyun #define SCLK_HDMI27M 191 214*4882a593Smuzhiyun #define SCLK_HDMIPHY 192 215*4882a593Smuzhiyun #define SCLK_USBPHY0 193 216*4882a593Smuzhiyun #define SCLK_USBPHY1 194 217*4882a593Smuzhiyun 218*4882a593Smuzhiyun /* S5P6442-specific clocks */ 219*4882a593Smuzhiyun #define MOUT_D0SYNC 195 220*4882a593Smuzhiyun #define MOUT_D1SYNC 196 221*4882a593Smuzhiyun #define DOUT_MIXER 197 222*4882a593Smuzhiyun #define CLK_ETB 198 223*4882a593Smuzhiyun #define CLK_ETM 199 224*4882a593Smuzhiyun 225*4882a593Smuzhiyun /* CLKOUT */ 226*4882a593Smuzhiyun #define FOUT_APLL_CLKOUT 200 227*4882a593Smuzhiyun #define FOUT_MPLL_CLKOUT 201 228*4882a593Smuzhiyun #define DOUT_APLL_CLKOUT 202 229*4882a593Smuzhiyun #define MOUT_CLKSEL 203 230*4882a593Smuzhiyun #define DOUT_CLKOUT 204 231*4882a593Smuzhiyun #define MOUT_CLKOUT 205 232*4882a593Smuzhiyun 233*4882a593Smuzhiyun /* Total number of clocks. */ 234*4882a593Smuzhiyun #define NR_CLKS 206 235*4882a593Smuzhiyun 236*4882a593Smuzhiyun #endif /* _DT_BINDINGS_CLOCK_S5PV210_H */ 237