1*4882a593Smuzhiyun /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2016 Rockchip Electronics Co. Ltd. 4*4882a593Smuzhiyun * Author: Shawn Lin <shawn.lin@rock-chips.com> 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H 8*4882a593Smuzhiyun #define _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* pll id */ 11*4882a593Smuzhiyun #define PLL_APLL 0 12*4882a593Smuzhiyun #define PLL_DPLL 1 13*4882a593Smuzhiyun #define PLL_GPLL 2 14*4882a593Smuzhiyun #define ARMCLK 3 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* sclk gates (special clocks) */ 17*4882a593Smuzhiyun #define SCLK_SPI0 65 18*4882a593Smuzhiyun #define SCLK_NANDC 67 19*4882a593Smuzhiyun #define SCLK_SDMMC 68 20*4882a593Smuzhiyun #define SCLK_SDIO 69 21*4882a593Smuzhiyun #define SCLK_EMMC 71 22*4882a593Smuzhiyun #define SCLK_UART0 72 23*4882a593Smuzhiyun #define SCLK_UART1 73 24*4882a593Smuzhiyun #define SCLK_UART2 74 25*4882a593Smuzhiyun #define SCLK_I2S0 75 26*4882a593Smuzhiyun #define SCLK_I2S1 76 27*4882a593Smuzhiyun #define SCLK_I2S2 77 28*4882a593Smuzhiyun #define SCLK_TIMER0 78 29*4882a593Smuzhiyun #define SCLK_TIMER1 79 30*4882a593Smuzhiyun #define SCLK_SFC 80 31*4882a593Smuzhiyun #define SCLK_SDMMC_DRV 81 32*4882a593Smuzhiyun #define SCLK_SDIO_DRV 82 33*4882a593Smuzhiyun #define SCLK_EMMC_DRV 83 34*4882a593Smuzhiyun #define SCLK_SDMMC_SAMPLE 84 35*4882a593Smuzhiyun #define SCLK_SDIO_SAMPLE 85 36*4882a593Smuzhiyun #define SCLK_EMMC_SAMPLE 86 37*4882a593Smuzhiyun #define SCLK_VENC_CORE 87 38*4882a593Smuzhiyun #define SCLK_HEVC_CORE 88 39*4882a593Smuzhiyun #define SCLK_HEVC_CABAC 89 40*4882a593Smuzhiyun #define SCLK_PWM0_PMU 90 41*4882a593Smuzhiyun #define SCLK_I2C0_PMU 91 42*4882a593Smuzhiyun #define SCLK_WIFI 92 43*4882a593Smuzhiyun #define SCLK_CIFOUT 93 44*4882a593Smuzhiyun #define SCLK_MIPI_CSI_OUT 94 45*4882a593Smuzhiyun #define SCLK_CIF0 95 46*4882a593Smuzhiyun #define SCLK_CIF1 96 47*4882a593Smuzhiyun #define SCLK_CIF2 97 48*4882a593Smuzhiyun #define SCLK_CIF3 98 49*4882a593Smuzhiyun #define SCLK_DSP 99 50*4882a593Smuzhiyun #define SCLK_DSP_IOP 100 51*4882a593Smuzhiyun #define SCLK_DSP_EPP 101 52*4882a593Smuzhiyun #define SCLK_DSP_EDP 102 53*4882a593Smuzhiyun #define SCLK_DSP_EDAP 103 54*4882a593Smuzhiyun #define SCLK_CVBS_HOST 104 55*4882a593Smuzhiyun #define SCLK_HDMI_SFR 105 56*4882a593Smuzhiyun #define SCLK_HDMI_CEC 106 57*4882a593Smuzhiyun #define SCLK_CRYPTO 107 58*4882a593Smuzhiyun #define SCLK_SPI 108 59*4882a593Smuzhiyun #define SCLK_SARADC 109 60*4882a593Smuzhiyun #define SCLK_TSADC 110 61*4882a593Smuzhiyun #define SCLK_MAC_PRE 111 62*4882a593Smuzhiyun #define SCLK_MAC 112 63*4882a593Smuzhiyun #define SCLK_MAC_RX 113 64*4882a593Smuzhiyun #define SCLK_MAC_REF 114 65*4882a593Smuzhiyun #define SCLK_MAC_REFOUT 115 66*4882a593Smuzhiyun #define SCLK_DSP_PFM 116 67*4882a593Smuzhiyun #define SCLK_RGA 117 68*4882a593Smuzhiyun #define SCLK_I2C1 118 69*4882a593Smuzhiyun #define SCLK_I2C2 119 70*4882a593Smuzhiyun #define SCLK_I2C3 120 71*4882a593Smuzhiyun #define SCLK_PWM 121 72*4882a593Smuzhiyun #define SCLK_ISP 122 73*4882a593Smuzhiyun #define SCLK_USBPHY 123 74*4882a593Smuzhiyun #define SCLK_I2S0_SRC 124 75*4882a593Smuzhiyun #define SCLK_I2S1_SRC 125 76*4882a593Smuzhiyun #define SCLK_I2S2_SRC 126 77*4882a593Smuzhiyun #define SCLK_UART0_SRC 127 78*4882a593Smuzhiyun #define SCLK_UART1_SRC 128 79*4882a593Smuzhiyun #define SCLK_UART2_SRC 129 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun #define DCLK_VOP_SRC 185 82*4882a593Smuzhiyun #define DCLK_HDMIPHY 186 83*4882a593Smuzhiyun #define DCLK_VOP 187 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun /* aclk gates */ 86*4882a593Smuzhiyun #define ACLK_DMAC 192 87*4882a593Smuzhiyun #define ACLK_PRE 193 88*4882a593Smuzhiyun #define ACLK_CORE 194 89*4882a593Smuzhiyun #define ACLK_ENMCORE 195 90*4882a593Smuzhiyun #define ACLK_RKVENC 196 91*4882a593Smuzhiyun #define ACLK_RKVDEC 197 92*4882a593Smuzhiyun #define ACLK_VPU 198 93*4882a593Smuzhiyun #define ACLK_CIF0 199 94*4882a593Smuzhiyun #define ACLK_VIO0 200 95*4882a593Smuzhiyun #define ACLK_VIO1 201 96*4882a593Smuzhiyun #define ACLK_VOP 202 97*4882a593Smuzhiyun #define ACLK_IEP 203 98*4882a593Smuzhiyun #define ACLK_RGA 204 99*4882a593Smuzhiyun #define ACLK_ISP 205 100*4882a593Smuzhiyun #define ACLK_CIF1 206 101*4882a593Smuzhiyun #define ACLK_CIF2 207 102*4882a593Smuzhiyun #define ACLK_CIF3 208 103*4882a593Smuzhiyun #define ACLK_PERI 209 104*4882a593Smuzhiyun #define ACLK_GMAC 210 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun /* pclk gates */ 107*4882a593Smuzhiyun #define PCLK_GPIO1 256 108*4882a593Smuzhiyun #define PCLK_GPIO2 257 109*4882a593Smuzhiyun #define PCLK_GPIO3 258 110*4882a593Smuzhiyun #define PCLK_GRF 259 111*4882a593Smuzhiyun #define PCLK_I2C1 260 112*4882a593Smuzhiyun #define PCLK_I2C2 261 113*4882a593Smuzhiyun #define PCLK_I2C3 262 114*4882a593Smuzhiyun #define PCLK_SPI 263 115*4882a593Smuzhiyun #define PCLK_SFC 264 116*4882a593Smuzhiyun #define PCLK_UART0 265 117*4882a593Smuzhiyun #define PCLK_UART1 266 118*4882a593Smuzhiyun #define PCLK_UART2 267 119*4882a593Smuzhiyun #define PCLK_TSADC 268 120*4882a593Smuzhiyun #define PCLK_PWM 269 121*4882a593Smuzhiyun #define PCLK_TIMER 270 122*4882a593Smuzhiyun #define PCLK_PERI 271 123*4882a593Smuzhiyun #define PCLK_GPIO0_PMU 272 124*4882a593Smuzhiyun #define PCLK_I2C0_PMU 273 125*4882a593Smuzhiyun #define PCLK_PWM0_PMU 274 126*4882a593Smuzhiyun #define PCLK_ISP 275 127*4882a593Smuzhiyun #define PCLK_VIO 276 128*4882a593Smuzhiyun #define PCLK_MIPI_DSI 277 129*4882a593Smuzhiyun #define PCLK_HDMI_CTRL 278 130*4882a593Smuzhiyun #define PCLK_SARADC 279 131*4882a593Smuzhiyun #define PCLK_DSP_CFG 280 132*4882a593Smuzhiyun #define PCLK_BUS 281 133*4882a593Smuzhiyun #define PCLK_EFUSE0 282 134*4882a593Smuzhiyun #define PCLK_EFUSE1 283 135*4882a593Smuzhiyun #define PCLK_WDT 284 136*4882a593Smuzhiyun #define PCLK_GMAC 285 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun /* hclk gates */ 139*4882a593Smuzhiyun #define HCLK_I2S0_8CH 320 140*4882a593Smuzhiyun #define HCLK_I2S1_2CH 321 141*4882a593Smuzhiyun #define HCLK_I2S2_2CH 322 142*4882a593Smuzhiyun #define HCLK_NANDC 323 143*4882a593Smuzhiyun #define HCLK_SDMMC 324 144*4882a593Smuzhiyun #define HCLK_SDIO 325 145*4882a593Smuzhiyun #define HCLK_EMMC 326 146*4882a593Smuzhiyun #define HCLK_PERI 327 147*4882a593Smuzhiyun #define HCLK_SFC 328 148*4882a593Smuzhiyun #define HCLK_RKVENC 329 149*4882a593Smuzhiyun #define HCLK_RKVDEC 330 150*4882a593Smuzhiyun #define HCLK_CIF0 331 151*4882a593Smuzhiyun #define HCLK_VIO 332 152*4882a593Smuzhiyun #define HCLK_VOP 333 153*4882a593Smuzhiyun #define HCLK_IEP 334 154*4882a593Smuzhiyun #define HCLK_RGA 335 155*4882a593Smuzhiyun #define HCLK_ISP 336 156*4882a593Smuzhiyun #define HCLK_CRYPTO_MST 337 157*4882a593Smuzhiyun #define HCLK_CRYPTO_SLV 338 158*4882a593Smuzhiyun #define HCLK_HOST0 339 159*4882a593Smuzhiyun #define HCLK_OTG 340 160*4882a593Smuzhiyun #define HCLK_CIF1 341 161*4882a593Smuzhiyun #define HCLK_CIF2 342 162*4882a593Smuzhiyun #define HCLK_CIF3 343 163*4882a593Smuzhiyun #define HCLK_BUS 344 164*4882a593Smuzhiyun #define HCLK_VPU 345 165*4882a593Smuzhiyun 166*4882a593Smuzhiyun #define CLK_NR_CLKS (HCLK_VPU + 1) 167*4882a593Smuzhiyun 168*4882a593Smuzhiyun /* reset id */ 169*4882a593Smuzhiyun #define SRST_CORE_PO_AD 0 170*4882a593Smuzhiyun #define SRST_CORE_AD 1 171*4882a593Smuzhiyun #define SRST_L2_AD 2 172*4882a593Smuzhiyun #define SRST_CPU_NIU_AD 3 173*4882a593Smuzhiyun #define SRST_CORE_PO 4 174*4882a593Smuzhiyun #define SRST_CORE 5 175*4882a593Smuzhiyun #define SRST_L2 6 176*4882a593Smuzhiyun #define SRST_CORE_DBG 8 177*4882a593Smuzhiyun #define PRST_DBG 9 178*4882a593Smuzhiyun #define RST_DAP 10 179*4882a593Smuzhiyun #define PRST_DBG_NIU 11 180*4882a593Smuzhiyun #define ARST_STRC_SYS_AD 15 181*4882a593Smuzhiyun 182*4882a593Smuzhiyun #define SRST_DDRPHY_CLKDIV 16 183*4882a593Smuzhiyun #define SRST_DDRPHY 17 184*4882a593Smuzhiyun #define PRST_DDRPHY 18 185*4882a593Smuzhiyun #define PRST_HDMIPHY 19 186*4882a593Smuzhiyun #define PRST_VDACPHY 20 187*4882a593Smuzhiyun #define PRST_VADCPHY 21 188*4882a593Smuzhiyun #define PRST_MIPI_CSI_PHY 22 189*4882a593Smuzhiyun #define PRST_MIPI_DSI_PHY 23 190*4882a593Smuzhiyun #define PRST_ACODEC 24 191*4882a593Smuzhiyun #define ARST_BUS_NIU 25 192*4882a593Smuzhiyun #define PRST_TOP_NIU 26 193*4882a593Smuzhiyun #define ARST_INTMEM 27 194*4882a593Smuzhiyun #define HRST_ROM 28 195*4882a593Smuzhiyun #define ARST_DMAC 29 196*4882a593Smuzhiyun #define SRST_MSCH_NIU 30 197*4882a593Smuzhiyun #define PRST_MSCH_NIU 31 198*4882a593Smuzhiyun 199*4882a593Smuzhiyun #define PRST_DDRUPCTL 32 200*4882a593Smuzhiyun #define NRST_DDRUPCTL 33 201*4882a593Smuzhiyun #define PRST_DDRMON 34 202*4882a593Smuzhiyun #define HRST_I2S0_8CH 35 203*4882a593Smuzhiyun #define MRST_I2S0_8CH 36 204*4882a593Smuzhiyun #define HRST_I2S1_2CH 37 205*4882a593Smuzhiyun #define MRST_IS21_2CH 38 206*4882a593Smuzhiyun #define HRST_I2S2_2CH 39 207*4882a593Smuzhiyun #define MRST_I2S2_2CH 40 208*4882a593Smuzhiyun #define HRST_CRYPTO 41 209*4882a593Smuzhiyun #define SRST_CRYPTO 42 210*4882a593Smuzhiyun #define PRST_SPI 43 211*4882a593Smuzhiyun #define SRST_SPI 44 212*4882a593Smuzhiyun #define PRST_UART0 45 213*4882a593Smuzhiyun #define PRST_UART1 46 214*4882a593Smuzhiyun #define PRST_UART2 47 215*4882a593Smuzhiyun 216*4882a593Smuzhiyun #define SRST_UART0 48 217*4882a593Smuzhiyun #define SRST_UART1 49 218*4882a593Smuzhiyun #define SRST_UART2 50 219*4882a593Smuzhiyun #define PRST_I2C1 51 220*4882a593Smuzhiyun #define PRST_I2C2 52 221*4882a593Smuzhiyun #define PRST_I2C3 53 222*4882a593Smuzhiyun #define SRST_I2C1 54 223*4882a593Smuzhiyun #define SRST_I2C2 55 224*4882a593Smuzhiyun #define SRST_I2C3 56 225*4882a593Smuzhiyun #define PRST_PWM1 58 226*4882a593Smuzhiyun #define SRST_PWM1 60 227*4882a593Smuzhiyun #define PRST_WDT 61 228*4882a593Smuzhiyun #define PRST_GPIO1 62 229*4882a593Smuzhiyun #define PRST_GPIO2 63 230*4882a593Smuzhiyun 231*4882a593Smuzhiyun #define PRST_GPIO3 64 232*4882a593Smuzhiyun #define PRST_GRF 65 233*4882a593Smuzhiyun #define PRST_EFUSE 66 234*4882a593Smuzhiyun #define PRST_EFUSE512 67 235*4882a593Smuzhiyun #define PRST_TIMER0 68 236*4882a593Smuzhiyun #define SRST_TIMER0 69 237*4882a593Smuzhiyun #define SRST_TIMER1 70 238*4882a593Smuzhiyun #define PRST_TSADC 71 239*4882a593Smuzhiyun #define SRST_TSADC 72 240*4882a593Smuzhiyun #define PRST_SARADC 73 241*4882a593Smuzhiyun #define SRST_SARADC 74 242*4882a593Smuzhiyun #define HRST_SYSBUS 75 243*4882a593Smuzhiyun #define PRST_USBGRF 76 244*4882a593Smuzhiyun 245*4882a593Smuzhiyun #define ARST_PERIPH_NIU 80 246*4882a593Smuzhiyun #define HRST_PERIPH_NIU 81 247*4882a593Smuzhiyun #define PRST_PERIPH_NIU 82 248*4882a593Smuzhiyun #define HRST_PERIPH 83 249*4882a593Smuzhiyun #define HRST_SDMMC 84 250*4882a593Smuzhiyun #define HRST_SDIO 85 251*4882a593Smuzhiyun #define HRST_EMMC 86 252*4882a593Smuzhiyun #define HRST_NANDC 87 253*4882a593Smuzhiyun #define NRST_NANDC 88 254*4882a593Smuzhiyun #define HRST_SFC 89 255*4882a593Smuzhiyun #define SRST_SFC 90 256*4882a593Smuzhiyun #define ARST_GMAC 91 257*4882a593Smuzhiyun #define HRST_OTG 92 258*4882a593Smuzhiyun #define SRST_OTG 93 259*4882a593Smuzhiyun #define SRST_OTG_ADP 94 260*4882a593Smuzhiyun #define HRST_HOST0 95 261*4882a593Smuzhiyun 262*4882a593Smuzhiyun #define HRST_HOST0_AUX 96 263*4882a593Smuzhiyun #define HRST_HOST0_ARB 97 264*4882a593Smuzhiyun #define SRST_HOST0_EHCIPHY 98 265*4882a593Smuzhiyun #define SRST_HOST0_UTMI 99 266*4882a593Smuzhiyun #define SRST_USBPOR 100 267*4882a593Smuzhiyun #define SRST_UTMI0 101 268*4882a593Smuzhiyun #define SRST_UTMI1 102 269*4882a593Smuzhiyun 270*4882a593Smuzhiyun #define ARST_VIO0_NIU 102 271*4882a593Smuzhiyun #define ARST_VIO1_NIU 103 272*4882a593Smuzhiyun #define HRST_VIO_NIU 104 273*4882a593Smuzhiyun #define PRST_VIO_NIU 105 274*4882a593Smuzhiyun #define ARST_VOP 106 275*4882a593Smuzhiyun #define HRST_VOP 107 276*4882a593Smuzhiyun #define DRST_VOP 108 277*4882a593Smuzhiyun #define ARST_IEP 109 278*4882a593Smuzhiyun #define HRST_IEP 110 279*4882a593Smuzhiyun #define ARST_RGA 111 280*4882a593Smuzhiyun #define HRST_RGA 112 281*4882a593Smuzhiyun #define SRST_RGA 113 282*4882a593Smuzhiyun #define PRST_CVBS 114 283*4882a593Smuzhiyun #define PRST_HDMI 115 284*4882a593Smuzhiyun #define SRST_HDMI 116 285*4882a593Smuzhiyun #define PRST_MIPI_DSI 117 286*4882a593Smuzhiyun 287*4882a593Smuzhiyun #define ARST_ISP_NIU 118 288*4882a593Smuzhiyun #define HRST_ISP_NIU 119 289*4882a593Smuzhiyun #define HRST_ISP 120 290*4882a593Smuzhiyun #define SRST_ISP 121 291*4882a593Smuzhiyun #define ARST_VIP0 122 292*4882a593Smuzhiyun #define HRST_VIP0 123 293*4882a593Smuzhiyun #define PRST_VIP0 124 294*4882a593Smuzhiyun #define ARST_VIP1 125 295*4882a593Smuzhiyun #define HRST_VIP1 126 296*4882a593Smuzhiyun #define PRST_VIP1 127 297*4882a593Smuzhiyun #define ARST_VIP2 128 298*4882a593Smuzhiyun #define HRST_VIP2 129 299*4882a593Smuzhiyun #define PRST_VIP2 120 300*4882a593Smuzhiyun #define ARST_VIP3 121 301*4882a593Smuzhiyun #define HRST_VIP3 122 302*4882a593Smuzhiyun #define PRST_VIP4 123 303*4882a593Smuzhiyun 304*4882a593Smuzhiyun #define PRST_CIF1TO4 124 305*4882a593Smuzhiyun #define SRST_CVBS_CLK 125 306*4882a593Smuzhiyun #define HRST_CVBS 126 307*4882a593Smuzhiyun 308*4882a593Smuzhiyun #define ARST_VPU_NIU 140 309*4882a593Smuzhiyun #define HRST_VPU_NIU 141 310*4882a593Smuzhiyun #define ARST_VPU 142 311*4882a593Smuzhiyun #define HRST_VPU 143 312*4882a593Smuzhiyun #define ARST_RKVDEC_NIU 144 313*4882a593Smuzhiyun #define HRST_RKVDEC_NIU 145 314*4882a593Smuzhiyun #define ARST_RKVDEC 146 315*4882a593Smuzhiyun #define HRST_RKVDEC 147 316*4882a593Smuzhiyun #define SRST_RKVDEC_CABAC 148 317*4882a593Smuzhiyun #define SRST_RKVDEC_CORE 149 318*4882a593Smuzhiyun #define ARST_RKVENC_NIU 150 319*4882a593Smuzhiyun #define HRST_RKVENC_NIU 151 320*4882a593Smuzhiyun #define ARST_RKVENC 152 321*4882a593Smuzhiyun #define HRST_RKVENC 153 322*4882a593Smuzhiyun #define SRST_RKVENC_CORE 154 323*4882a593Smuzhiyun 324*4882a593Smuzhiyun #define SRST_DSP_CORE 156 325*4882a593Smuzhiyun #define SRST_DSP_SYS 157 326*4882a593Smuzhiyun #define SRST_DSP_GLOBAL 158 327*4882a593Smuzhiyun #define SRST_DSP_OECM 159 328*4882a593Smuzhiyun #define PRST_DSP_IOP_NIU 160 329*4882a593Smuzhiyun #define ARST_DSP_EPP_NIU 161 330*4882a593Smuzhiyun #define ARST_DSP_EDP_NIU 162 331*4882a593Smuzhiyun #define PRST_DSP_DBG_NIU 163 332*4882a593Smuzhiyun #define PRST_DSP_CFG_NIU 164 333*4882a593Smuzhiyun #define PRST_DSP_GRF 165 334*4882a593Smuzhiyun #define PRST_DSP_MAILBOX 166 335*4882a593Smuzhiyun #define PRST_DSP_INTC 167 336*4882a593Smuzhiyun #define PRST_DSP_PFM_MON 169 337*4882a593Smuzhiyun #define SRST_DSP_PFM_MON 170 338*4882a593Smuzhiyun #define ARST_DSP_EDAP_NIU 171 339*4882a593Smuzhiyun 340*4882a593Smuzhiyun #define SRST_PMU 172 341*4882a593Smuzhiyun #define SRST_PMU_I2C0 173 342*4882a593Smuzhiyun #define PRST_PMU_I2C0 174 343*4882a593Smuzhiyun #define PRST_PMU_GPIO0 175 344*4882a593Smuzhiyun #define PRST_PMU_INTMEM 176 345*4882a593Smuzhiyun #define PRST_PMU_PWM0 177 346*4882a593Smuzhiyun #define SRST_PMU_PWM0 178 347*4882a593Smuzhiyun #define PRST_PMU_GRF 179 348*4882a593Smuzhiyun #define SRST_PMU_NIU 180 349*4882a593Smuzhiyun #define SRST_PMU_PVTM 181 350*4882a593Smuzhiyun #define ARST_DSP_EDP_PERF 184 351*4882a593Smuzhiyun #define ARST_DSP_EPP_PERF 185 352*4882a593Smuzhiyun 353*4882a593Smuzhiyun #endif /* _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H */ 354