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Searched refs:PHY_REG (Results 1 – 19 of 19) sorted by relevance

/OK3568_Linux_fs/u-boot/drivers/ram/rockchip/
H A Dsdram_phy_px30.c19 setbits_le32(PHY_REG(phy_base, 0x13), 1 << 4); in sdram_phy_dll_bypass_set()
20 clrbits_le32(PHY_REG(phy_base, 0x14), 1 << 3); in sdram_phy_dll_bypass_set()
23 setbits_le32(PHY_REG(phy_base, j), 1 << 4); in sdram_phy_dll_bypass_set()
24 clrbits_le32(PHY_REG(phy_base, j + 0x1), 1 << 3); in sdram_phy_dll_bypass_set()
29 setbits_le32(PHY_REG(phy_base, 0xa4), 0x1f); in sdram_phy_dll_bypass_set()
31 clrbits_le32(PHY_REG(phy_base, 0xa4), 0x1f); in sdram_phy_dll_bypass_set()
46 writel(tmp, PHY_REG(phy_base, j)); in sdram_phy_dll_bypass_set()
71 writel(cmd_drv, PHY_REG(phy_base, 0x11)); in sdram_phy_set_ds_odt()
72 clrsetbits_le32(PHY_REG(phy_base, 0x12), 0x1f << 3, cmd_drv << 3); in sdram_phy_set_ds_odt()
73 writel(clk_drv, PHY_REG(phy_base, 0x16)); in sdram_phy_set_ds_odt()
[all …]
H A Dsdram_rv1126.c565 clrbits_le32(PHY_REG(phy_base, 0x53), PHY_PD_DISB); in phy_pll_set()
566 while (!(readl(PHY_REG(phy_base, 0x90)) & PHY_PLL_LOCK)) { in phy_pll_set()
590 writel(fbdiv & 0xff, PHY_REG(phy_base, 0x50)); in phy_pll_set()
591 clrsetbits_le32(PHY_REG(phy_base, 0x51), PHY_PBDIV_BIT9_MASK, in phy_pll_set()
593 clrsetbits_le32(PHY_REG(phy_base, 0x51), PHY_POSTDIV_EN_MASK, in phy_pll_set()
596 clrsetbits_le32(PHY_REG(phy_base, 0x52), in phy_pll_set()
598 clrsetbits_le32(PHY_REG(phy_base, 0x53), in phy_pll_set()
1037 clrsetbits_le32(PHY_REG(phy_base, 0x100), 0x1f, phy_ca_drv); in set_ds_odt()
1038 clrsetbits_le32(PHY_REG(phy_base, 0x101), 0x1f, phy_ca_drv); in set_ds_odt()
1039 clrsetbits_le32(PHY_REG(phy_base, 0x102), 0x1f, phy_clk_drv); in set_ds_odt()
[all …]
H A Dsdram_rk3328.c126 clrbits_le32(PHY_REG(phy_base, 0xef), 1 << 7); in rkclk_configure_ddr()
266 gate_val = MAX(readl(PHY_REG(phy_base, 0xfb + i)), gate_val); in rx_deskew_switch_adjust()
270 clrsetbits_le32(PHY_REG(phy_base, 0x6e), 0xc, (deskew_val & 0x3) << 2); in rx_deskew_switch_adjust()
271 clrsetbits_le32(PHY_REG(phy_base, 0x6f), 0x7 << 4, in rx_deskew_switch_adjust()
279 clrsetbits_le32(PHY_REG(phy_base, 0x6e), 0x3, 1); in tx_deskew_switch_adjust()
H A Dsdram_px30.c248 bw = (readl(PHY_REG(phy_base, 0x0)) >> 4) & 0xf; in check_rd_gate()
263 gate[i] = readl(PHY_REG(phy_base, 0xfb + i)); in check_rd_gate()
386 setbits_le32(PHY_REG(phy_base, 7), 1 << 7); in enable_low_power()
/OK3568_Linux_fs/kernel/drivers/net/ethernet/intel/e1000e/
H A Dich8lan.h107 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \ macro
109 #define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */
110 #define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */
117 #define BM_PORT_GEN_CFG PHY_REG(BM_PORT_CTRL_PAGE, 17)
118 #define BM_RCTL PHY_REG(BM_WUC_PAGE, 0)
119 #define BM_WUC PHY_REG(BM_WUC_PAGE, 1)
120 #define BM_WUFC PHY_REG(BM_WUC_PAGE, 2)
121 #define BM_WUS PHY_REG(BM_WUC_PAGE, 3)
136 #define HV_LED_CONFIG PHY_REG(768, 30) /* LED Configuration */
137 #define HV_MUX_DATA_CTRL PHY_REG(776, 16)
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H A Dethtool.c1361 e1e_rphy(hw, PHY_REG(2, 21), &phy_reg); in e1000_integrated_phy_loopback()
1364 e1e_wphy(hw, PHY_REG(2, 21), phy_reg); in e1000_integrated_phy_loopback()
1369 e1e_rphy(hw, PHY_REG(769, 16), &phy_reg); in e1000_integrated_phy_loopback()
1370 e1e_wphy(hw, PHY_REG(769, 16), phy_reg | 0x000C); in e1000_integrated_phy_loopback()
1372 e1e_rphy(hw, PHY_REG(776, 16), &phy_reg); in e1000_integrated_phy_loopback()
1373 e1e_wphy(hw, PHY_REG(776, 16), phy_reg | 0x0040); in e1000_integrated_phy_loopback()
1375 e1e_rphy(hw, PHY_REG(769, 16), &phy_reg); in e1000_integrated_phy_loopback()
1376 e1e_wphy(hw, PHY_REG(769, 16), phy_reg | 0x0040); in e1000_integrated_phy_loopback()
1378 e1e_rphy(hw, PHY_REG(769, 20), &phy_reg); in e1000_integrated_phy_loopback()
1379 e1e_wphy(hw, PHY_REG(769, 20), phy_reg | 0x0400); in e1000_integrated_phy_loopback()
[all …]
H A Dich8lan.c1492 PHY_REG(776, 20), in e1000_check_for_copper_link_ich8lan()
1505 PHY_REG(776, 20), in e1000_check_for_copper_link_ich8lan()
1517 PHY_REG(776, 20), in e1000_check_for_copper_link_ich8lan()
2275 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x0100); in e1000_k1_gig_workaround_hv()
2281 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x4100); in e1000_k1_gig_workaround_hv()
2460 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431); in e1000_hv_phy_workarounds_ich8lan()
2575 e1e_rphy(hw, PHY_REG(769, 20), &phy_reg); in e1000_lv_jumbo_workaround_ich8lan()
2576 ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | BIT(14)); in e1000_lv_jumbo_workaround_ich8lan()
2639 e1e_rphy(hw, PHY_REG(769, 23), &data); in e1000_lv_jumbo_workaround_ich8lan()
2642 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data); in e1000_lv_jumbo_workaround_ich8lan()
[all …]
H A Dregs.h242 #define I82579_DFT_CTRL PHY_REG(769, 20)
H A Dnetdev.c3086 e1e_rphy(hw, PHY_REG(770, 26), &phy_data); in e1000_setup_rctl()
3089 e1e_wphy(hw, PHY_REG(770, 26), phy_data); in e1000_setup_rctl()
/OK3568_Linux_fs/kernel/drivers/phy/rockchip/
H A Dphy-rockchip-dphy-rx0.c110 #define PHY_REG(_offset, _width, _shift) \ macro
114 [GRF_DPHY_RX0_TURNREQUEST] = PHY_REG(RK3399_GRF_SOC_CON9, 4, 0),
115 [GRF_DPHY_RX0_CLK_INV_SEL] = PHY_REG(RK3399_GRF_SOC_CON9, 1, 10),
116 [GRF_DPHY_RX1_CLK_INV_SEL] = PHY_REG(RK3399_GRF_SOC_CON9, 1, 11),
117 [GRF_DPHY_RX0_ENABLE] = PHY_REG(RK3399_GRF_SOC_CON21, 4, 0),
118 [GRF_DPHY_RX0_FORCERXMODE] = PHY_REG(RK3399_GRF_SOC_CON21, 4, 4),
119 [GRF_DPHY_RX0_FORCETXSTOPMODE] = PHY_REG(RK3399_GRF_SOC_CON21, 4, 8),
120 [GRF_DPHY_RX0_TURNDISABLE] = PHY_REG(RK3399_GRF_SOC_CON21, 4, 12),
121 [GRF_DPHY_TX0_FORCERXMODE] = PHY_REG(RK3399_GRF_SOC_CON22, 4, 0),
122 [GRF_DPHY_TX0_FORCETXSTOPMODE] = PHY_REG(RK3399_GRF_SOC_CON22, 4, 4),
[all …]
H A Dphy-rockchip-mipi-rx.c340 #define PHY_REG(_offset, _width, _shift) \ macro
350 [GRF_DPHY_CSIPHY_FORCERXMODE] = PHY_REG(RK1808_GRF_PD_VI_CON_OFFSET, 4, 0),
351 [GRF_DPHY_CSIPHY_CLKLANE_EN] = PHY_REG(RK1808_GRF_PD_VI_CON_OFFSET, 1, 8),
352 [GRF_DPHY_CSIPHY_DATALANE_EN] = PHY_REG(RK1808_GRF_PD_VI_CON_OFFSET, 4, 4),
356 [GRF_CON_DISABLE_ISP] = PHY_REG(RK3288_GRF_SOC_CON6, 1, 0),
357 [GRF_CON_ISP_DPHY_SEL] = PHY_REG(RK3288_GRF_SOC_CON6, 1, 1),
358 [GRF_DSI_CSI_TESTBUS_SEL] = PHY_REG(RK3288_GRF_SOC_CON6, 1, 14),
359 [GRF_DPHY_TX0_TURNDISABLE] = PHY_REG(RK3288_GRF_SOC_CON8, 4, 0),
360 [GRF_DPHY_TX0_FORCERXMODE] = PHY_REG(RK3288_GRF_SOC_CON8, 4, 4),
361 [GRF_DPHY_TX0_FORCETXSTOPMODE] = PHY_REG(RK3288_GRF_SOC_CON8, 4, 8),
[all …]
H A Dphy-rockchip-inno-video-combo-phy.c35 #define PHY_REG(first, second) (FIRST_ADDRESS(first) | \ macro
238 u32 reg = PHY_REG(first, second) << 2; in phy_update_bits()
H A Dphy-rockchip-inno-dsidphy.c37 #define PHY_REG(first, second) (FIRST_ADDRESS(first) | \ macro
309 u32 reg = PHY_REG(first, second) << 2; in phy_update_bits()
/OK3568_Linux_fs/kernel/drivers/net/dsa/
H A Dlan9303_mdio.c18 #define PHY_REG(x) (((x) >> 1) & 0x1f) macro
27 mdio->bus->write(mdio->bus, PHY_ADDR(reg), PHY_REG(reg), val); in lan9303_mdio_real_write()
45 return mdio->bus->read(mdio->bus, PHY_ADDR(reg), PHY_REG(reg)); in lan9303_mdio_real_read()
/OK3568_Linux_fs/kernel/drivers/net/ethernet/intel/e1000/
H A De1000_hw.h2915 #define PHY_REG(page, reg) \ macro
2919 PHY_REG(769, 17) /* Port General Configuration */
2921 PHY_REG(769, 25) /* Rate Adapter Control Register */
2924 PHY_REG(770, 16) /* KMRN FIFO's control/status register */
2926 PHY_REG(770, 17) /* KMRN Power Management Control Register */
2928 PHY_REG(770, 18) /* KMRN Inband Control Register */
2930 PHY_REG(770, 19) /* KMRN Diagnostic register */
2933 PHY_REG(770, 20) /* KMRN Acknowledge Timeouts register */
2936 PHY_REG(776, 18) /* Voltage regulator control register */
2941 PHY_REG(776, 19) /* IGP3 Capability Register */
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dsdram_phy_px30.h15 #define PHY_REG(base, n) ((base) + 4 * (n)) macro
H A Dsdram_phy_rv1126.h92 #define PHY_REG(base, n) ((base) + 4 * (n)) macro
/OK3568_Linux_fs/u-boot/drivers/video/drm/
H A Dinno_video_combo_phy.c35 #define PHY_REG(first, second) (FIRST_ADDRESS(first) | \ macro
330 u32 reg = PHY_REG(first, second) << 2; in phy_update_bits()
/OK3568_Linux_fs/kernel/drivers/net/wireless/realtek/rtlwifi/rtl8192se/
H A Dreg.h230 #define PHY_REG 0x02F3 macro