1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* Copyright(c) 1999 - 2018 Intel Corporation. */ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #ifndef _E1000E_REGS_H_ 5*4882a593Smuzhiyun #define _E1000E_REGS_H_ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #define E1000_CTRL 0x00000 /* Device Control - RW */ 8*4882a593Smuzhiyun #define E1000_STATUS 0x00008 /* Device Status - RO */ 9*4882a593Smuzhiyun #define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */ 10*4882a593Smuzhiyun #define E1000_EERD 0x00014 /* EEPROM Read - RW */ 11*4882a593Smuzhiyun #define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */ 12*4882a593Smuzhiyun #define E1000_FLA 0x0001C /* Flash Access - RW */ 13*4882a593Smuzhiyun #define E1000_MDIC 0x00020 /* MDI Control - RW */ 14*4882a593Smuzhiyun #define E1000_SCTL 0x00024 /* SerDes Control - RW */ 15*4882a593Smuzhiyun #define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */ 16*4882a593Smuzhiyun #define E1000_FCAH 0x0002C /* Flow Control Address High -RW */ 17*4882a593Smuzhiyun #define E1000_FEXT 0x0002C /* Future Extended - RW */ 18*4882a593Smuzhiyun #define E1000_FEXTNVM 0x00028 /* Future Extended NVM - RW */ 19*4882a593Smuzhiyun #define E1000_FEXTNVM3 0x0003C /* Future Extended NVM 3 - RW */ 20*4882a593Smuzhiyun #define E1000_FEXTNVM4 0x00024 /* Future Extended NVM 4 - RW */ 21*4882a593Smuzhiyun #define E1000_FEXTNVM5 0x00014 /* Future Extended NVM 5 - RW */ 22*4882a593Smuzhiyun #define E1000_FEXTNVM6 0x00010 /* Future Extended NVM 6 - RW */ 23*4882a593Smuzhiyun #define E1000_FEXTNVM7 0x000E4 /* Future Extended NVM 7 - RW */ 24*4882a593Smuzhiyun #define E1000_FEXTNVM8 0x5BB0 /* Future Extended NVM 8 - RW */ 25*4882a593Smuzhiyun #define E1000_FEXTNVM9 0x5BB4 /* Future Extended NVM 9 - RW */ 26*4882a593Smuzhiyun #define E1000_FEXTNVM11 0x5BBC /* Future Extended NVM 11 - RW */ 27*4882a593Smuzhiyun #define E1000_FEXTNVM12 0x5BC0 /* Future Extended NVM 12 - RW */ 28*4882a593Smuzhiyun #define E1000_PCIEANACFG 0x00F18 /* PCIE Analog Config */ 29*4882a593Smuzhiyun #define E1000_DPGFR 0x00FAC /* Dynamic Power Gate Force Control Register */ 30*4882a593Smuzhiyun #define E1000_FCT 0x00030 /* Flow Control Type - RW */ 31*4882a593Smuzhiyun #define E1000_VET 0x00038 /* VLAN Ether Type - RW */ 32*4882a593Smuzhiyun #define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */ 33*4882a593Smuzhiyun #define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */ 34*4882a593Smuzhiyun #define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */ 35*4882a593Smuzhiyun #define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */ 36*4882a593Smuzhiyun #define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */ 37*4882a593Smuzhiyun #define E1000_IAM 0x000E0 /* Interrupt Acknowledge Auto Mask */ 38*4882a593Smuzhiyun #define E1000_IVAR 0x000E4 /* Interrupt Vector Allocation Register - RW */ 39*4882a593Smuzhiyun #define E1000_SVCR 0x000F0 40*4882a593Smuzhiyun #define E1000_SVT 0x000F4 41*4882a593Smuzhiyun #define E1000_LPIC 0x000FC /* Low Power IDLE control */ 42*4882a593Smuzhiyun #define E1000_RCTL 0x00100 /* Rx Control - RW */ 43*4882a593Smuzhiyun #define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */ 44*4882a593Smuzhiyun #define E1000_TXCW 0x00178 /* Tx Configuration Word - RW */ 45*4882a593Smuzhiyun #define E1000_RXCW 0x00180 /* Rx Configuration Word - RO */ 46*4882a593Smuzhiyun #define E1000_PBA_ECC 0x01100 /* PBA ECC Register */ 47*4882a593Smuzhiyun #define E1000_TCTL 0x00400 /* Tx Control - RW */ 48*4882a593Smuzhiyun #define E1000_TCTL_EXT 0x00404 /* Extended Tx Control - RW */ 49*4882a593Smuzhiyun #define E1000_TIPG 0x00410 /* Tx Inter-packet gap -RW */ 50*4882a593Smuzhiyun #define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */ 51*4882a593Smuzhiyun #define E1000_LEDCTL 0x00E00 /* LED Control - RW */ 52*4882a593Smuzhiyun #define E1000_EXTCNF_CTRL 0x00F00 /* Extended Configuration Control */ 53*4882a593Smuzhiyun #define E1000_EXTCNF_SIZE 0x00F08 /* Extended Configuration Size */ 54*4882a593Smuzhiyun #define E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */ 55*4882a593Smuzhiyun #define E1000_POEMB E1000_PHY_CTRL /* PHY OEM Bits */ 56*4882a593Smuzhiyun #define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */ 57*4882a593Smuzhiyun #define E1000_PBS 0x01008 /* Packet Buffer Size */ 58*4882a593Smuzhiyun #define E1000_PBECCSTS 0x0100C /* Packet Buffer ECC Status - RW */ 59*4882a593Smuzhiyun #define E1000_IOSFPC 0x00F28 /* TX corrupted data */ 60*4882a593Smuzhiyun #define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */ 61*4882a593Smuzhiyun #define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */ 62*4882a593Smuzhiyun #define E1000_FLOP 0x0103C /* FLASH Opcode Register */ 63*4882a593Smuzhiyun #define E1000_ERT 0x02008 /* Early Rx Threshold - RW */ 64*4882a593Smuzhiyun #define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */ 65*4882a593Smuzhiyun #define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */ 66*4882a593Smuzhiyun #define E1000_PSRCTL 0x02170 /* Packet Split Receive Control - RW */ 67*4882a593Smuzhiyun #define E1000_RDFH 0x02410 /* Rx Data FIFO Head - RW */ 68*4882a593Smuzhiyun #define E1000_RDFT 0x02418 /* Rx Data FIFO Tail - RW */ 69*4882a593Smuzhiyun #define E1000_RDFHS 0x02420 /* Rx Data FIFO Head Saved - RW */ 70*4882a593Smuzhiyun #define E1000_RDFTS 0x02428 /* Rx Data FIFO Tail Saved - RW */ 71*4882a593Smuzhiyun #define E1000_RDFPC 0x02430 /* Rx Data FIFO Packet Count - RW */ 72*4882a593Smuzhiyun /* Split and Replication Rx Control - RW */ 73*4882a593Smuzhiyun #define E1000_RDTR 0x02820 /* Rx Delay Timer - RW */ 74*4882a593Smuzhiyun #define E1000_RADV 0x0282C /* Rx Interrupt Absolute Delay Timer - RW */ 75*4882a593Smuzhiyun /* Convenience macros 76*4882a593Smuzhiyun * 77*4882a593Smuzhiyun * Note: "_n" is the queue number of the register to be written to. 78*4882a593Smuzhiyun * 79*4882a593Smuzhiyun * Example usage: 80*4882a593Smuzhiyun * E1000_RDBAL_REG(current_rx_queue) 81*4882a593Smuzhiyun */ 82*4882a593Smuzhiyun #define E1000_RDBAL(_n) ((_n) < 4 ? (0x02800 + ((_n) * 0x100)) : \ 83*4882a593Smuzhiyun (0x0C000 + ((_n) * 0x40))) 84*4882a593Smuzhiyun #define E1000_RDBAH(_n) ((_n) < 4 ? (0x02804 + ((_n) * 0x100)) : \ 85*4882a593Smuzhiyun (0x0C004 + ((_n) * 0x40))) 86*4882a593Smuzhiyun #define E1000_RDLEN(_n) ((_n) < 4 ? (0x02808 + ((_n) * 0x100)) : \ 87*4882a593Smuzhiyun (0x0C008 + ((_n) * 0x40))) 88*4882a593Smuzhiyun #define E1000_RDH(_n) ((_n) < 4 ? (0x02810 + ((_n) * 0x100)) : \ 89*4882a593Smuzhiyun (0x0C010 + ((_n) * 0x40))) 90*4882a593Smuzhiyun #define E1000_RDT(_n) ((_n) < 4 ? (0x02818 + ((_n) * 0x100)) : \ 91*4882a593Smuzhiyun (0x0C018 + ((_n) * 0x40))) 92*4882a593Smuzhiyun #define E1000_RXDCTL(_n) ((_n) < 4 ? (0x02828 + ((_n) * 0x100)) : \ 93*4882a593Smuzhiyun (0x0C028 + ((_n) * 0x40))) 94*4882a593Smuzhiyun #define E1000_TDBAL(_n) ((_n) < 4 ? (0x03800 + ((_n) * 0x100)) : \ 95*4882a593Smuzhiyun (0x0E000 + ((_n) * 0x40))) 96*4882a593Smuzhiyun #define E1000_TDBAH(_n) ((_n) < 4 ? (0x03804 + ((_n) * 0x100)) : \ 97*4882a593Smuzhiyun (0x0E004 + ((_n) * 0x40))) 98*4882a593Smuzhiyun #define E1000_TDLEN(_n) ((_n) < 4 ? (0x03808 + ((_n) * 0x100)) : \ 99*4882a593Smuzhiyun (0x0E008 + ((_n) * 0x40))) 100*4882a593Smuzhiyun #define E1000_TDH(_n) ((_n) < 4 ? (0x03810 + ((_n) * 0x100)) : \ 101*4882a593Smuzhiyun (0x0E010 + ((_n) * 0x40))) 102*4882a593Smuzhiyun #define E1000_TDT(_n) ((_n) < 4 ? (0x03818 + ((_n) * 0x100)) : \ 103*4882a593Smuzhiyun (0x0E018 + ((_n) * 0x40))) 104*4882a593Smuzhiyun #define E1000_TXDCTL(_n) ((_n) < 4 ? (0x03828 + ((_n) * 0x100)) : \ 105*4882a593Smuzhiyun (0x0E028 + ((_n) * 0x40))) 106*4882a593Smuzhiyun #define E1000_TARC(_n) (0x03840 + ((_n) * 0x100)) 107*4882a593Smuzhiyun #define E1000_KABGTXD 0x03004 /* AFE Band Gap Transmit Ref Data */ 108*4882a593Smuzhiyun #define E1000_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \ 109*4882a593Smuzhiyun (0x054E0 + ((_i - 16) * 8))) 110*4882a593Smuzhiyun #define E1000_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \ 111*4882a593Smuzhiyun (0x054E4 + ((_i - 16) * 8))) 112*4882a593Smuzhiyun #define E1000_SHRAL(_i) (0x05438 + ((_i) * 8)) 113*4882a593Smuzhiyun #define E1000_SHRAH(_i) (0x0543C + ((_i) * 8)) 114*4882a593Smuzhiyun #define E1000_TDFH 0x03410 /* Tx Data FIFO Head - RW */ 115*4882a593Smuzhiyun #define E1000_TDFT 0x03418 /* Tx Data FIFO Tail - RW */ 116*4882a593Smuzhiyun #define E1000_TDFHS 0x03420 /* Tx Data FIFO Head Saved - RW */ 117*4882a593Smuzhiyun #define E1000_TDFTS 0x03428 /* Tx Data FIFO Tail Saved - RW */ 118*4882a593Smuzhiyun #define E1000_TDFPC 0x03430 /* Tx Data FIFO Packet Count - RW */ 119*4882a593Smuzhiyun #define E1000_TIDV 0x03820 /* Tx Interrupt Delay Value - RW */ 120*4882a593Smuzhiyun #define E1000_TADV 0x0382C /* Tx Interrupt Absolute Delay Val - RW */ 121*4882a593Smuzhiyun #define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */ 122*4882a593Smuzhiyun #define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */ 123*4882a593Smuzhiyun #define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */ 124*4882a593Smuzhiyun #define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */ 125*4882a593Smuzhiyun #define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */ 126*4882a593Smuzhiyun #define E1000_SCC 0x04014 /* Single Collision Count - R/clr */ 127*4882a593Smuzhiyun #define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */ 128*4882a593Smuzhiyun #define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */ 129*4882a593Smuzhiyun #define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */ 130*4882a593Smuzhiyun #define E1000_COLC 0x04028 /* Collision Count - R/clr */ 131*4882a593Smuzhiyun #define E1000_DC 0x04030 /* Defer Count - R/clr */ 132*4882a593Smuzhiyun #define E1000_TNCRS 0x04034 /* Tx-No CRS - R/clr */ 133*4882a593Smuzhiyun #define E1000_SEC 0x04038 /* Sequence Error Count - R/clr */ 134*4882a593Smuzhiyun #define E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */ 135*4882a593Smuzhiyun #define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */ 136*4882a593Smuzhiyun #define E1000_XONRXC 0x04048 /* XON Rx Count - R/clr */ 137*4882a593Smuzhiyun #define E1000_XONTXC 0x0404C /* XON Tx Count - R/clr */ 138*4882a593Smuzhiyun #define E1000_XOFFRXC 0x04050 /* XOFF Rx Count - R/clr */ 139*4882a593Smuzhiyun #define E1000_XOFFTXC 0x04054 /* XOFF Tx Count - R/clr */ 140*4882a593Smuzhiyun #define E1000_FCRUC 0x04058 /* Flow Control Rx Unsupported Count- R/clr */ 141*4882a593Smuzhiyun #define E1000_PRC64 0x0405C /* Packets Rx (64 bytes) - R/clr */ 142*4882a593Smuzhiyun #define E1000_PRC127 0x04060 /* Packets Rx (65-127 bytes) - R/clr */ 143*4882a593Smuzhiyun #define E1000_PRC255 0x04064 /* Packets Rx (128-255 bytes) - R/clr */ 144*4882a593Smuzhiyun #define E1000_PRC511 0x04068 /* Packets Rx (255-511 bytes) - R/clr */ 145*4882a593Smuzhiyun #define E1000_PRC1023 0x0406C /* Packets Rx (512-1023 bytes) - R/clr */ 146*4882a593Smuzhiyun #define E1000_PRC1522 0x04070 /* Packets Rx (1024-1522 bytes) - R/clr */ 147*4882a593Smuzhiyun #define E1000_GPRC 0x04074 /* Good Packets Rx Count - R/clr */ 148*4882a593Smuzhiyun #define E1000_BPRC 0x04078 /* Broadcast Packets Rx Count - R/clr */ 149*4882a593Smuzhiyun #define E1000_MPRC 0x0407C /* Multicast Packets Rx Count - R/clr */ 150*4882a593Smuzhiyun #define E1000_GPTC 0x04080 /* Good Packets Tx Count - R/clr */ 151*4882a593Smuzhiyun #define E1000_GORCL 0x04088 /* Good Octets Rx Count Low - R/clr */ 152*4882a593Smuzhiyun #define E1000_GORCH 0x0408C /* Good Octets Rx Count High - R/clr */ 153*4882a593Smuzhiyun #define E1000_GOTCL 0x04090 /* Good Octets Tx Count Low - R/clr */ 154*4882a593Smuzhiyun #define E1000_GOTCH 0x04094 /* Good Octets Tx Count High - R/clr */ 155*4882a593Smuzhiyun #define E1000_RNBC 0x040A0 /* Rx No Buffers Count - R/clr */ 156*4882a593Smuzhiyun #define E1000_RUC 0x040A4 /* Rx Undersize Count - R/clr */ 157*4882a593Smuzhiyun #define E1000_RFC 0x040A8 /* Rx Fragment Count - R/clr */ 158*4882a593Smuzhiyun #define E1000_ROC 0x040AC /* Rx Oversize Count - R/clr */ 159*4882a593Smuzhiyun #define E1000_RJC 0x040B0 /* Rx Jabber Count - R/clr */ 160*4882a593Smuzhiyun #define E1000_MGTPRC 0x040B4 /* Management Packets Rx Count - R/clr */ 161*4882a593Smuzhiyun #define E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */ 162*4882a593Smuzhiyun #define E1000_MGTPTC 0x040BC /* Management Packets Tx Count - R/clr */ 163*4882a593Smuzhiyun #define E1000_TORL 0x040C0 /* Total Octets Rx Low - R/clr */ 164*4882a593Smuzhiyun #define E1000_TORH 0x040C4 /* Total Octets Rx High - R/clr */ 165*4882a593Smuzhiyun #define E1000_TOTL 0x040C8 /* Total Octets Tx Low - R/clr */ 166*4882a593Smuzhiyun #define E1000_TOTH 0x040CC /* Total Octets Tx High - R/clr */ 167*4882a593Smuzhiyun #define E1000_TPR 0x040D0 /* Total Packets Rx - R/clr */ 168*4882a593Smuzhiyun #define E1000_TPT 0x040D4 /* Total Packets Tx - R/clr */ 169*4882a593Smuzhiyun #define E1000_PTC64 0x040D8 /* Packets Tx (64 bytes) - R/clr */ 170*4882a593Smuzhiyun #define E1000_PTC127 0x040DC /* Packets Tx (65-127 bytes) - R/clr */ 171*4882a593Smuzhiyun #define E1000_PTC255 0x040E0 /* Packets Tx (128-255 bytes) - R/clr */ 172*4882a593Smuzhiyun #define E1000_PTC511 0x040E4 /* Packets Tx (256-511 bytes) - R/clr */ 173*4882a593Smuzhiyun #define E1000_PTC1023 0x040E8 /* Packets Tx (512-1023 bytes) - R/clr */ 174*4882a593Smuzhiyun #define E1000_PTC1522 0x040EC /* Packets Tx (1024-1522 Bytes) - R/clr */ 175*4882a593Smuzhiyun #define E1000_MPTC 0x040F0 /* Multicast Packets Tx Count - R/clr */ 176*4882a593Smuzhiyun #define E1000_BPTC 0x040F4 /* Broadcast Packets Tx Count - R/clr */ 177*4882a593Smuzhiyun #define E1000_TSCTC 0x040F8 /* TCP Segmentation Context Tx - R/clr */ 178*4882a593Smuzhiyun #define E1000_TSCTFC 0x040FC /* TCP Segmentation Context Tx Fail - R/clr */ 179*4882a593Smuzhiyun #define E1000_IAC 0x04100 /* Interrupt Assertion Count */ 180*4882a593Smuzhiyun #define E1000_ICRXPTC 0x04104 /* Interrupt Cause Rx Pkt Timer Expire Count */ 181*4882a593Smuzhiyun #define E1000_ICRXATC 0x04108 /* Interrupt Cause Rx Abs Timer Expire Count */ 182*4882a593Smuzhiyun #define E1000_ICTXPTC 0x0410C /* Interrupt Cause Tx Pkt Timer Expire Count */ 183*4882a593Smuzhiyun #define E1000_ICTXATC 0x04110 /* Interrupt Cause Tx Abs Timer Expire Count */ 184*4882a593Smuzhiyun #define E1000_ICTXQEC 0x04118 /* Interrupt Cause Tx Queue Empty Count */ 185*4882a593Smuzhiyun #define E1000_ICTXQMTC 0x0411C /* Interrupt Cause Tx Queue Min Thresh Count */ 186*4882a593Smuzhiyun #define E1000_ICRXDMTC 0x04120 /* Interrupt Cause Rx Desc Min Thresh Count */ 187*4882a593Smuzhiyun #define E1000_ICRXOC 0x04124 /* Interrupt Cause Receiver Overrun Count */ 188*4882a593Smuzhiyun #define E1000_CRC_OFFSET 0x05F50 /* CRC Offset register */ 189*4882a593Smuzhiyun 190*4882a593Smuzhiyun #define E1000_PCS_LCTL 0x04208 /* PCS Link Control - RW */ 191*4882a593Smuzhiyun #define E1000_PCS_LSTAT 0x0420C /* PCS Link Status - RO */ 192*4882a593Smuzhiyun #define E1000_PCS_ANADV 0x04218 /* AN advertisement - RW */ 193*4882a593Smuzhiyun #define E1000_PCS_LPAB 0x0421C /* Link Partner Ability - RW */ 194*4882a593Smuzhiyun #define E1000_RXCSUM 0x05000 /* Rx Checksum Control - RW */ 195*4882a593Smuzhiyun #define E1000_RFCTL 0x05008 /* Receive Filter Control */ 196*4882a593Smuzhiyun #define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */ 197*4882a593Smuzhiyun #define E1000_RA 0x05400 /* Receive Address - RW Array */ 198*4882a593Smuzhiyun #define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */ 199*4882a593Smuzhiyun #define E1000_WUC 0x05800 /* Wakeup Control - RW */ 200*4882a593Smuzhiyun #define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */ 201*4882a593Smuzhiyun #define E1000_WUS 0x05810 /* Wakeup Status - RO */ 202*4882a593Smuzhiyun #define E1000_MANC 0x05820 /* Management Control - RW */ 203*4882a593Smuzhiyun #define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */ 204*4882a593Smuzhiyun #define E1000_HOST_IF 0x08800 /* Host Interface */ 205*4882a593Smuzhiyun 206*4882a593Smuzhiyun #define E1000_KMRNCTRLSTA 0x00034 /* MAC-PHY interface - RW */ 207*4882a593Smuzhiyun #define E1000_MANC2H 0x05860 /* Management Control To Host - RW */ 208*4882a593Smuzhiyun /* Management Decision Filters */ 209*4882a593Smuzhiyun #define E1000_MDEF(_n) (0x05890 + (4 * (_n))) 210*4882a593Smuzhiyun #define E1000_SW_FW_SYNC 0x05B5C /* SW-FW Synchronization - RW */ 211*4882a593Smuzhiyun #define E1000_GCR 0x05B00 /* PCI-Ex Control */ 212*4882a593Smuzhiyun #define E1000_GCR2 0x05B64 /* PCI-Ex Control #2 */ 213*4882a593Smuzhiyun #define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */ 214*4882a593Smuzhiyun #define E1000_SWSM 0x05B50 /* SW Semaphore */ 215*4882a593Smuzhiyun #define E1000_FWSM 0x05B54 /* FW Semaphore */ 216*4882a593Smuzhiyun /* Driver-only SW semaphore (not used by BOOT agents) */ 217*4882a593Smuzhiyun #define E1000_SWSM2 0x05B58 218*4882a593Smuzhiyun #define E1000_FFLT_DBG 0x05F04 /* Debug Register */ 219*4882a593Smuzhiyun #define E1000_HICR 0x08F00 /* Host Interface Control */ 220*4882a593Smuzhiyun 221*4882a593Smuzhiyun /* RSS registers */ 222*4882a593Smuzhiyun #define E1000_MRQC 0x05818 /* Multiple Receive Control - RW */ 223*4882a593Smuzhiyun #define E1000_RETA(_i) (0x05C00 + ((_i) * 4)) /* Redirection Table - RW */ 224*4882a593Smuzhiyun #define E1000_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* RSS Random Key - RW */ 225*4882a593Smuzhiyun #define E1000_TSYNCRXCTL 0x0B620 /* Rx Time Sync Control register - RW */ 226*4882a593Smuzhiyun #define E1000_TSYNCTXCTL 0x0B614 /* Tx Time Sync Control register - RW */ 227*4882a593Smuzhiyun #define E1000_RXSTMPL 0x0B624 /* Rx timestamp Low - RO */ 228*4882a593Smuzhiyun #define E1000_RXSTMPH 0x0B628 /* Rx timestamp High - RO */ 229*4882a593Smuzhiyun #define E1000_TXSTMPL 0x0B618 /* Tx timestamp value Low - RO */ 230*4882a593Smuzhiyun #define E1000_TXSTMPH 0x0B61C /* Tx timestamp value High - RO */ 231*4882a593Smuzhiyun #define E1000_SYSTIML 0x0B600 /* System time register Low - RO */ 232*4882a593Smuzhiyun #define E1000_SYSTIMH 0x0B604 /* System time register High - RO */ 233*4882a593Smuzhiyun #define E1000_TIMINCA 0x0B608 /* Increment attributes register - RW */ 234*4882a593Smuzhiyun #define E1000_SYSSTMPL 0x0B648 /* HH Timesync system stamp low register */ 235*4882a593Smuzhiyun #define E1000_SYSSTMPH 0x0B64C /* HH Timesync system stamp hi register */ 236*4882a593Smuzhiyun #define E1000_PLTSTMPL 0x0B640 /* HH Timesync platform stamp low register */ 237*4882a593Smuzhiyun #define E1000_PLTSTMPH 0x0B644 /* HH Timesync platform stamp hi register */ 238*4882a593Smuzhiyun #define E1000_RXMTRL 0x0B634 /* Time sync Rx EtherType and Msg Type - RW */ 239*4882a593Smuzhiyun #define E1000_RXUDP 0x0B638 /* Time Sync Rx UDP Port - RW */ 240*4882a593Smuzhiyun 241*4882a593Smuzhiyun /* PHY registers */ 242*4882a593Smuzhiyun #define I82579_DFT_CTRL PHY_REG(769, 20) 243*4882a593Smuzhiyun 244*4882a593Smuzhiyun #endif 245