Lines Matching refs:PHY_REG
565 clrbits_le32(PHY_REG(phy_base, 0x53), PHY_PD_DISB); in phy_pll_set()
566 while (!(readl(PHY_REG(phy_base, 0x90)) & PHY_PLL_LOCK)) { in phy_pll_set()
590 writel(fbdiv & 0xff, PHY_REG(phy_base, 0x50)); in phy_pll_set()
591 clrsetbits_le32(PHY_REG(phy_base, 0x51), PHY_PBDIV_BIT9_MASK, in phy_pll_set()
593 clrsetbits_le32(PHY_REG(phy_base, 0x51), PHY_POSTDIV_EN_MASK, in phy_pll_set()
596 clrsetbits_le32(PHY_REG(phy_base, 0x52), in phy_pll_set()
598 clrsetbits_le32(PHY_REG(phy_base, 0x53), in phy_pll_set()
1037 clrsetbits_le32(PHY_REG(phy_base, 0x100), 0x1f, phy_ca_drv); in set_ds_odt()
1038 clrsetbits_le32(PHY_REG(phy_base, 0x101), 0x1f, phy_ca_drv); in set_ds_odt()
1039 clrsetbits_le32(PHY_REG(phy_base, 0x102), 0x1f, phy_clk_drv); in set_ds_odt()
1040 clrsetbits_le32(PHY_REG(phy_base, 0x103), 0x1f, phy_clk_drv); in set_ds_odt()
1042 clrsetbits_le32(PHY_REG(phy_base, 0x107), 0x1f, phy_clk_drv); in set_ds_odt()
1043 clrsetbits_le32(PHY_REG(phy_base, 0x108), 0x1f, phy_clk_drv); in set_ds_odt()
1045 clrsetbits_le32(PHY_REG(phy_base, 0x107), 0x1f, phy_ca_drv); in set_ds_odt()
1046 clrsetbits_le32(PHY_REG(phy_base, 0x108), 0x1f, phy_ca_drv); in set_ds_odt()
1049 clrsetbits_le32(PHY_REG(phy_base, 0x106), 0x1f, sr_clk); in set_ds_odt()
1059 clrsetbits_le32(PHY_REG(phy_base, j + 1), 0x1f, phy_odt_up); in set_ds_odt()
1060 clrsetbits_le32(PHY_REG(phy_base, j), 0x1f, phy_odt_dn); in set_ds_odt()
1061 clrsetbits_le32(PHY_REG(phy_base, j + 2), 0x1f, phy_dq_drv); in set_ds_odt()
1062 clrsetbits_le32(PHY_REG(phy_base, j + 3), 0x1f, phy_dq_drv); in set_ds_odt()
1063 writel(vref_inner, PHY_REG(phy_base, 0x118 + i * 0x10)); in set_ds_odt()
1065 clrsetbits_le32(PHY_REG(phy_base, 0x114 + i * 0x10), in set_ds_odt()
1068 clrbits_le32(PHY_REG(phy_base, 0x114 + i * 0x10), BIT(5)); in set_ds_odt()
1070 clrsetbits_le32(PHY_REG(phy_base, 0x117 + i * 0x10), in set_ds_odt()
1075 setbits_le32(PHY_REG(phy_base, 0x71), 1 << 5); in set_ds_odt()
1076 clrbits_le32(PHY_REG(phy_base, 0x71), 1 << 5); in set_ds_odt()
1079 writel(vref_out, PHY_REG(phy_base, 0x105)); in set_ds_odt()
1236 PHY_REG(phy_base, 0x4f)); in sdram_cmd_dq_path_remap()
1257 clrbits_le32(PHY_REG(phy_base, 0x62), BIT(5)); in phy_cfg()
1258 dq_map = readl(PHY_REG(phy_base, 0x4f)); in phy_cfg()
1272 tmp = readl(PHY_REG(phy_base, 0xf)) & (~PHY_DQ_WIDTH_MASK); in phy_cfg()
1280 writel(tmp, PHY_REG(phy_base, 0xf)); in phy_cfg()
1285 clrsetbits_le32(PHY_REG(phy_base, 0x20), 0x7 << 4, in phy_cfg()
1288 setbits_le32(PHY_REG(phy_base, 0x1e), BIT(6)); in phy_cfg()
1289 setbits_le32(PHY_REG(phy_base, 0x1f), BIT(6)); in phy_cfg()
1291 clrbits_le32(PHY_REG(phy_base, 0x7c), BIT(5)); in phy_cfg()
1376 writel(dq_sel[i][0], PHY_REG(phy_base, in record_dq_prebit()
1378 tmp = readl(PHY_REG(phy_base, grp_addr[group] + 0x2e)); in record_dq_prebit()
1379 writel(tmp, PHY_REG(phy_base, in record_dq_prebit()
1383 writel(dq_sel[i][0], PHY_REG(phy_base, in record_dq_prebit()
1385 tmp = readl(PHY_REG(phy_base, grp_addr[group] + 0x2f)); in record_dq_prebit()
1386 writel(tmp, PHY_REG(phy_base, in record_dq_prebit()
1396 clrsetbits_le32(PHY_REG(phy_base, 0x70), BIT(1) | BIT(6) | BIT(4), in update_dq_rx_prebit()
1399 clrbits_le32(PHY_REG(phy_base, 0x70), BIT(4)); in update_dq_rx_prebit()
1406 clrbits_le32(PHY_REG(phy_base, 0x7a), BIT(1)); in update_dq_tx_prebit()
1407 setbits_le32(PHY_REG(phy_base, 0x2), BIT(3)); in update_dq_tx_prebit()
1408 setbits_le32(PHY_REG(phy_base, 0xc), BIT(6)); in update_dq_tx_prebit()
1410 clrbits_le32(PHY_REG(phy_base, 0xc), BIT(6)); in update_dq_tx_prebit()
1417 clrbits_le32(PHY_REG(phy_base, 0x25), BIT(2)); in update_ca_prebit()
1418 setbits_le32(PHY_REG(phy_base, 0x22), BIT(6)); in update_ca_prebit()
1420 clrbits_le32(PHY_REG(phy_base, 0x22), BIT(6)); in update_ca_prebit()
1444 ((readl(PHY_REG(phy_base, 0x60)) & BIT(5)) == 0)) { in modify_ca_deskew()
1446 setbits_le32(PHY_REG(phy_base, 0x60), BIT(5)); in modify_ca_deskew()
1454 tmp = readl(PHY_REG(phy_base, 0x150 + i)) + in modify_ca_deskew()
1456 writel(tmp, PHY_REG(phy_base, 0x150 + i)); in modify_ca_deskew()
1462 tmp = readl(PHY_REG(phy_base, 0x150 + 0x17)) - in modify_ca_deskew()
1464 writel(tmp, PHY_REG(phy_base, 0x150 + 0x17)); in modify_ca_deskew()
1465 writel(tmp, PHY_REG(phy_base, 0x150 + 0x18)); in modify_ca_deskew()
1467 writel(tmp, PHY_REG(phy_base, 0x150 + 0x4)); in modify_ca_deskew()
1468 writel(tmp, PHY_REG(phy_base, 0x150 + 0xa)); in modify_ca_deskew()
1470 clrbits_le32(PHY_REG(phy_base, 0x10), cs_en << 6); in modify_ca_deskew()
1476 clrbits_le32(PHY_REG(phy_base, 0x60), BIT(5)); in modify_ca_deskew()
1492 min = MIN(min, readl(PHY_REG(phy_base, 0x150 + i))); in get_min_value()
1494 byte_en = readl(PHY_REG(phy_base, 0xf)) & 0xf; in get_min_value()
1500 readl(PHY_REG(phy_base, in get_min_value()
1538 byte_en = readl(PHY_REG(phy_base, 0xf)) & 0xf; in modify_dq_deskew()
1552 tmp = delta_sig + readl(PHY_REG(phy_base, in modify_dq_deskew()
1555 writel(tmp, PHY_REG(phy_base, dqs_dq_skew_adr[j] + i)); in modify_dq_deskew()
1560 tmp = delta_dif + readl(PHY_REG(phy_base, in modify_dq_deskew()
1562 writel(tmp, PHY_REG(phy_base, dqs_dq_skew_adr[j] + 9)); in modify_dq_deskew()
1563 writel(tmp, PHY_REG(phy_base, dqs_dq_skew_adr[j] + 0xa)); in modify_dq_deskew()
1579 odt_val_dn = readl(PHY_REG(phy_base, 0x110)); in data_training_rg()
1580 odt_val_up = readl(PHY_REG(phy_base, 0x111)); in data_training_rg()
1586 PHY_REG(phy_base, j)); in data_training_rg()
1588 PHY_REG(phy_base, j + 0x1)); in data_training_rg()
1593 clrbits_le32(PHY_REG(phy_base, 0xc), BIT(1)); in data_training_rg()
1596 setbits_le32(PHY_REG(phy_base, 0xc), BIT(1)); in data_training_rg()
1599 clrsetbits_le32(PHY_REG(phy_base, 2), 0x33, (0x20 >> cs)); in data_training_rg()
1601 clrsetbits_le32(PHY_REG(phy_base, 2), 0x33, (0x20 >> cs) | 1); in data_training_rg()
1603 ret = readl(PHY_REG(phy_base, 0x91)); in data_training_rg()
1605 clrsetbits_le32(PHY_REG(phy_base, 2), 0x33, (0x20 >> cs) | 0); in data_training_rg()
1606 clrbits_le32(PHY_REG(phy_base, 2), 0x30); in data_training_rg()
1609 ret = (ret & 0x2f) ^ (readl(PHY_REG(phy_base, 0xf)) & 0xf); in data_training_rg()
1614 writel(odt_val_dn, PHY_REG(phy_base, j)); in data_training_rg()
1615 writel(odt_val_up, PHY_REG(phy_base, j + 0x1)); in data_training_rg()
1633 clrbits_le32(PHY_REG(phy_base, 0x7a), 0x1); in data_training_wl()
1638 writel(tmp & 0xff, PHY_REG(phy_base, 0x3)); in data_training_wl()
1645 writel(0x40 | ((tmp >> 8) & 0x3f), PHY_REG(phy_base, 0x4)); in data_training_wl()
1647 writel(0x80 | ((tmp >> 8) & 0x3f), PHY_REG(phy_base, 0x4)); in data_training_wl()
1650 clrsetbits_le32(PHY_REG(phy_base, 2), (0x3 << 6) | (0x3 << 2), in data_training_wl()
1653 clrsetbits_le32(PHY_REG(phy_base, 2), (0x3 << 6) | (0x3 << 2), in data_training_wl()
1657 if ((readl(PHY_REG(phy_base, 0x92)) & 0xf) == in data_training_wl()
1658 (readl(PHY_REG(phy_base, 0xf)) & 0xf)) in data_training_wl()
1670 clrsetbits_le32(PHY_REG(phy_base, 2), (0x3 << 6) | (0x3 << 2), in data_training_wl()
1672 clrsetbits_le32(PHY_REG(phy_base, 2), 0x3 << 6, 0 << 6); in data_training_wl()
1707 vref_inner = readl(PHY_REG(phy_base, 0x128)) & 0xff; in data_training_rd()
1711 PHY_REG(phy_base, 0x118 + i * 0x10)); in data_training_rd()
1714 setbits_le32(PHY_REG(phy_base, 0x71), 1 << 5); in data_training_rd()
1715 clrbits_le32(PHY_REG(phy_base, 0x71), 1 << 5); in data_training_rd()
1734 clrsetbits_le32(PHY_REG(phy_base, 0x6e), 0xff, trefi_1x & 0xff); in data_training_rd()
1735 clrsetbits_le32(PHY_REG(phy_base, 0x6f), 0x3f, (trefi_1x >> 8) & 0x3f); in data_training_rd()
1737 clrsetbits_le32(PHY_REG(phy_base, 0x57), 0xff, trfc_1x); in data_training_rd()
1739 clrsetbits_le32(PHY_REG(phy_base, 0x61), 0xf << 4, 0x8 << 4); in data_training_rd()
1742 clrsetbits_le32(PHY_REG(phy_base, 0x71), 0x3 << 6, (0x2 >> cs) << 6); in data_training_rd()
1746 setbits_le32(PHY_REG(phy_base, 0x70), BIT(7)); in data_training_rd()
1750 PHY_REG(phy_base, 0x238 + i)); in data_training_rd()
1753 PHY_REG(phy_base, 0x2b8 + i)); in data_training_rd()
1758 clrsetbits_le32(PHY_REG(phy_base, 0x230), 0x3f, dqs_default); in data_training_rd()
1760 clrsetbits_le32(PHY_REG(phy_base, 0x234), 0x3f, dqs_default); in data_training_rd()
1762 clrsetbits_le32(PHY_REG(phy_base, 0x2b0), 0x3f, dqs_default); in data_training_rd()
1764 clrsetbits_le32(PHY_REG(phy_base, 0x2b4), 0x3f, dqs_default); in data_training_rd()
1767 clrsetbits_le32(PHY_REG(phy_base, 0x70), 0x3, 0x1); in data_training_rd()
1769 clrsetbits_le32(PHY_REG(phy_base, 0x70), 0x3, 0x3); in data_training_rd()
1773 if ((readl(PHY_REG(phy_base, 0x93)) >> 7) & 0x1) in data_training_rd()
1784 if ((readl(PHY_REG(phy_base, 0x240)) & 0x3) || in data_training_rd()
1785 (readl(PHY_REG(phy_base, 0x2c0)) & 0x3)) { in data_training_rd()
1791 clrbits_le32(PHY_REG(phy_base, 0x70), BIT(1)); in data_training_rd()
1798 PHY_REG(phy_base, 0x118 + i * 0x10)); in data_training_rd()
1801 setbits_le32(PHY_REG(phy_base, 0x71), 1 << 5); in data_training_rd()
1802 clrbits_le32(PHY_REG(phy_base, 0x71), 1 << 5); in data_training_rd()
1820 phy_fsp = (readl(PHY_REG(phy_base, 0xc)) >> 0x2) & 0x3; in data_training_wr()
1822 cl = readl(PHY_REG(phy_base, offset)); in data_training_wr()
1823 cwl = readl(PHY_REG(phy_base, offset + 2)); in data_training_wr()
1825 clrsetbits_le32(PHY_REG(phy_base, offset), 0x1f, 0x8); in data_training_wr()
1826 clrsetbits_le32(PHY_REG(phy_base, offset + 2), 0x1f, 0x4); in data_training_wr()
1833 clrsetbits_le32(PHY_REG(phy_base, 0x7b), 0xff, 0x0); in data_training_wr()
1835 clrsetbits_le32(PHY_REG(phy_base, 0x7c), 0x7 << 2, 0x0 << 2); in data_training_wr()
1837 clrsetbits_le32(PHY_REG(phy_base, 0x7c), 0x3, 0x0); in data_training_wr()
1839 clrsetbits_le32(PHY_REG(phy_base, 0x7d), 0xff, 0x0); in data_training_wr()
1841 clrsetbits_le32(PHY_REG(phy_base, 0x7e), 0xff, 0x0); in data_training_wr()
1844 clrbits_le32(PHY_REG(phy_base, 0x71), BIT(3)); in data_training_wr()
1853 clrsetbits_le32(PHY_REG(phy_base, 0x6e), 0xff, trefi_1x & 0xff); in data_training_wr()
1854 clrsetbits_le32(PHY_REG(phy_base, 0x6f), 0x3f, (trefi_1x >> 8) & 0x3f); in data_training_wr()
1856 clrsetbits_le32(PHY_REG(phy_base, 0x57), 0xff, trfc_1x); in data_training_wr()
1858 clrsetbits_le32(PHY_REG(phy_base, 0x61), 0xf << 4, 0x8 << 4); in data_training_wr()
1861 clrsetbits_le32(PHY_REG(phy_base, 0x7c), 0x3 << 6, (0x2 >> cs) << 6); in data_training_wr()
1866 setbits_le32(PHY_REG(phy_base, 0x7a), BIT(4)); in data_training_wr()
1869 setbits_le32(PHY_REG(phy_base, 0x7a), 0x1); in data_training_wr()
1872 setbits_le32(PHY_REG(phy_base, 0x7a), BIT(1)); in data_training_wr()
1877 if ((readl(PHY_REG(phy_base, 0x92)) >> 7) & 0x1) in data_training_wr()
1889 if ((readl(PHY_REG(phy_base, 0x90)) >> 5) & 0x7) { in data_training_wr()
1895 clrbits_le32(PHY_REG(phy_base, 0x7a), BIT(1)); in data_training_wr()
1902 ((readl(PHY_REG(phy_base, 0x384)) & 0x3f) + in data_training_wr()
1903 (readl(PHY_REG(phy_base, 0x385)) & 0x3f)) / 2; in data_training_wr()
1906 ((readl(PHY_REG(phy_base, 0x7c)) & BIT(5)) << 1); in data_training_wr()
1910 clrsetbits_le32(PHY_REG(phy_base, offset), 0x1f, cl); in data_training_wr()
1911 clrsetbits_le32(PHY_REG(phy_base, offset + 2), 0x1f, cwl); in data_training_wr()
1987 (readl(PHY_REG(phy_base, wrlvl_result_offset[j][i])) & 0x3f) - in get_wrlvl_val()
2002 result->byte_en = readb(PHY_REG(dram_info.phy, 0xf)) & in init_rw_trn_result_struct()
2027 readb(PHY_REG(phy_base, phy_ofs + 0x15 + dq)); in save_rw_trn_min_max()
2029 readb(PHY_REG(phy_base, phy_ofs + 0x27 + dq)); in save_rw_trn_min_max()
2031 readb(PHY_REG(phy_base, phy_ofs + 0x3d + dq)); in save_rw_trn_min_max()
2033 readb(PHY_REG(phy_base, phy_ofs + 0x4f + dq)); in save_rw_trn_min_max()
2053 readb(PHY_REG(phy_base, phy_ofs + dq)); in save_rw_trn_deskew()
2055 readb(PHY_REG(phy_base, phy_ofs + 0xb + dq)); in save_rw_trn_deskew()
2057 readb(PHY_REG(phy_base, phy_ofs + 0x60 + dq)); in save_rw_trn_deskew()
2059 readb(PHY_REG(phy_base, phy_ofs + 0x60 + 0xb + dq)); in save_rw_trn_deskew()
2063 readb(PHY_REG(phy_base, phy_ofs + 0x8)); in save_rw_trn_deskew()
2065 readb(PHY_REG(phy_base, phy_ofs + 0xb + 0x8)); in save_rw_trn_deskew()
2067 readb(PHY_REG(phy_base, phy_ofs + 0x60 + 0x8)); in save_rw_trn_deskew()
2069 readb(PHY_REG(phy_base, phy_ofs + 0x60 + 0xb + 0x8)); in save_rw_trn_deskew()
2092 byte_en = readl(PHY_REG(phy_base, 0xf)) & PHY_DQ_WIDTH_MASK; in high_freq_training()
2129 writel(wrlvl_result[0][0] + clk_skew, PHY_REG(phy_base, 0x233)); in high_freq_training()
2130 writel(wrlvl_result[0][1] + clk_skew, PHY_REG(phy_base, 0x237)); in high_freq_training()
2131 writel(wrlvl_result[0][2] + clk_skew, PHY_REG(phy_base, 0x2b3)); in high_freq_training()
2132 writel(wrlvl_result[0][3] + clk_skew, PHY_REG(phy_base, 0x2b7)); in high_freq_training()
2142 writel(wrlvl_result[1][0] + clk_skew, PHY_REG(phy_base, 0x233)); in high_freq_training()
2143 writel(wrlvl_result[1][1] + clk_skew, PHY_REG(phy_base, 0x237)); in high_freq_training()
2144 writel(wrlvl_result[1][2] + clk_skew, PHY_REG(phy_base, 0x2b3)); in high_freq_training()
2145 writel(wrlvl_result[1][3] + clk_skew, PHY_REG(phy_base, 0x2b7)); in high_freq_training()
2581 setbits_le32(PHY_REG(phy_base, 0xf), 0xf); in sdram_init_()
2622 ddr4_vref = readl(PHY_REG(phy_base, 0x105)) * 39; in sdram_init_()
2718 setbits_le32(PHY_REG(phy_base, 0xf), 0xf); in dram_detect_cap()
2724 dq_map = readl(PHY_REG(phy_base, 0x4f)); in dram_detect_cap()
2731 clrsetbits_le32(PHY_REG(phy_base, 0xf), PHY_DQ_WIDTH_MASK, in dram_detect_cap()
2978 phy_offset = PHY_REG(0, 0x387 - 5 + (dst_fsp - 1) * 3); in pre_set_rate()
3006 PHY_REG(phy_base, 0x1b)); in pre_set_rate()
3013 PHY_REG(phy_base, 0x19)); in pre_set_rate()
3023 PHY_REG(phy_base, 0x17)); in pre_set_rate()
3028 PHY_REG(phy_base, 0x18)); in pre_set_rate()
3037 PHY_REG(phy_base, 0x1a)); in pre_set_rate()
3050 PHY_REG(phy_base, 0x1d)); in pre_set_rate()
3056 PHY_REG(phy_base, 0x1c)); in pre_set_rate()
3087 p_fsp_param->rd_odt = readl(PHY_REG(phy_base, 0x111)); in save_fsp_param()
3089 p_fsp_param->rd_odt = readl(PHY_REG(phy_base, 0x110)); in save_fsp_param()
3092 p_fsp_param->wr_dq_drv = readl(PHY_REG(phy_base, 0x112)); in save_fsp_param()
3093 p_fsp_param->wr_ca_drv = readl(PHY_REG(phy_base, 0x100)); in save_fsp_param()
3094 p_fsp_param->wr_ckcs_drv = readl(PHY_REG(phy_base, 0x102)); in save_fsp_param()
3095 p_fsp_param->vref_inner = readl(PHY_REG(phy_base, 0x128)); in save_fsp_param()
3096 p_fsp_param->vref_out = readl(PHY_REG(phy_base, 0x105)); in save_fsp_param()
3133 temp = MAX(readl(PHY_REG(phy_base, 0x3ae)), in save_fsp_param()
3134 readl(PHY_REG(phy_base, 0x3ce))); in save_fsp_param()
3135 temp1 = MIN(readl(PHY_REG(phy_base, 0x3be)), in save_fsp_param()
3136 readl(PHY_REG(phy_base, 0x3de))); in save_fsp_param()
3138 temp = MAX(readl(PHY_REG(phy_base, 0x3af)), in save_fsp_param()
3139 readl(PHY_REG(phy_base, 0x3cf))); in save_fsp_param()
3140 temp1 = MIN(readl(PHY_REG(phy_base, 0x3bf)), in save_fsp_param()
3141 readl(PHY_REG(phy_base, 0x3df))); in save_fsp_param()
3144 (readl(PHY_REG(phy_base, 0x1e)) & BIT(6)); in save_fsp_param()
3146 (readl(PHY_REG(phy_base, 0x1e)) & BIT(6)); in save_fsp_param()
3148 p_fsp_param->lp4_drv_pd_en = (readl(PHY_REG(phy_base, 0x114)) >> in save_fsp_param()
3391 clrbits_le32(PHY_REG(phy_base, 0), ANALOG_DERESET | DIGITAL_DERESET); in ddr_set_rate()
3395 setbits_le32(PHY_REG(phy_base, 0), ANALOG_DERESET | DIGITAL_DERESET); in ddr_set_rate()
3421 clrsetbits_le32(PHY_REG(phy_base, 0xc), 0x3 << 2, dst_fsp << 2); in ddr_set_rate()
3425 setbits_le32(PHY_REG(phy_base, 0x71), 1 << 5); in ddr_set_rate()
3426 clrbits_le32(PHY_REG(phy_base, 0x71), 1 << 5); in ddr_set_rate()