1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2008-2018 Fuzhou Rockchip Electronics Co., Ltd
4 *
5 * Author: Wyon Bi <bivvy.bi@rock-chips.com>
6 */
7
8 #include <asm/arch/cpu.h>
9 #include <config.h>
10 #include <common.h>
11 #include <errno.h>
12 #include <dm.h>
13 #include <div64.h>
14 #include <asm/io.h>
15 #include <linux/ioport.h>
16 #include <linux/iopoll.h>
17 #include <linux/math64.h>
18
19 #include "rockchip_phy.h"
20
21 #define USEC_PER_SEC 1000000LL
22 #define PSEC_PER_SEC 1000000000000LL
23
24 #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l)))
25
26 /*
27 * The offset address[7:0] is distributed two parts, one from the bit7 to bit5
28 * is the first address, the other from the bit4 to bit0 is the second address.
29 * when you configure the registers, you must set both of them. The Clock Lane
30 * and Data Lane use the same registers with the same second address, but the
31 * first address is different.
32 */
33 #define FIRST_ADDRESS(x) (((x) & 0x7) << 5)
34 #define SECOND_ADDRESS(x) (((x) & 0x1f) << 0)
35 #define PHY_REG(first, second) (FIRST_ADDRESS(first) | \
36 SECOND_ADDRESS(second))
37
38 /* Analog Register Part: reg00 */
39 #define BANDGAP_POWER_MASK BIT(7)
40 #define BANDGAP_POWER_DOWN BIT(7)
41 #define BANDGAP_POWER_ON 0
42 #define LANE_EN_MASK GENMASK(6, 2)
43 #define LANE_EN_CK BIT(6)
44 #define LANE_EN_3 BIT(5)
45 #define LANE_EN_2 BIT(4)
46 #define LANE_EN_1 BIT(3)
47 #define LANE_EN_0 BIT(2)
48 #define POWER_WORK_MASK GENMASK(1, 0)
49 #define POWER_WORK_ENABLE UPDATE(1, 1, 0)
50 #define POWER_WORK_DISABLE UPDATE(2, 1, 0)
51 /* Analog Register Part: reg01 */
52 #define REG_SYNCRST_MASK BIT(2)
53 #define REG_SYNCRST_RESET BIT(2)
54 #define REG_SYNCRST_NORMAL 0
55 #define REG_LDOPD_MASK BIT(1)
56 #define REG_LDOPD_POWER_DOWN BIT(1)
57 #define REG_LDOPD_POWER_ON 0
58 #define REG_PLLPD_MASK BIT(0)
59 #define REG_PLLPD_POWER_DOWN BIT(0)
60 #define REG_PLLPD_POWER_ON 0
61 /* Analog Register Part: reg03 */
62 #define REG_FBDIV_HI_MASK BIT(5)
63 #define REG_FBDIV_HI(x) UPDATE(x, 5, 5)
64 #define REG_PREDIV_MASK GENMASK(4, 0)
65 #define REG_PREDIV(x) UPDATE(x, 4, 0)
66 /* Analog Register Part: reg04 */
67 #define REG_FBDIV_LO_MASK GENMASK(7, 0)
68 #define REG_FBDIV_LO(x) UPDATE(x, 7, 0)
69 /* Analog Register Part: reg05 */
70 #define SAMPLE_CLOCK_PHASE_MASK GENMASK(6, 4)
71 #define SAMPLE_CLOCK_PHASE(x) UPDATE(x, 6, 4)
72 #define CLOCK_LANE_SKEW_PHASE_MASK GENMASK(2, 0)
73 #define CLOCK_LANE_SKEW_PHASE(x) UPDATE(x, 2, 0)
74 /* Analog Register Part: reg06 */
75 #define DATA_LANE_3_SKEW_PHASE_MASK GENMASK(6, 4)
76 #define DATA_LANE_3_SKEW_PHASE(x) UPDATE(x, 6, 4)
77 #define DATA_LANE_2_SKEW_PHASE_MASK GENMASK(2, 0)
78 #define DATA_LANE_2_SKEW_PHASE(x) UPDATE(x, 2, 0)
79 /* Analog Register Part: reg07 */
80 #define DATA_LANE_1_SKEW_PHASE_MASK GENMASK(6, 4)
81 #define DATA_LANE_1_SKEW_PHASE(x) UPDATE(x, 6, 4)
82 #define DATA_LANE_0_SKEW_PHASE_MASK GENMASK(2, 0)
83 #define DATA_LANE_0_SKEW_PHASE(x) UPDATE(x, 2, 0)
84 /* Analog Register Part: reg08 */
85 #define PRE_EMPHASIS_ENABLE_MASK BIT(7)
86 #define PRE_EMPHASIS_ENABLE BIT(7)
87 #define PRE_EMPHASIS_DISABLE 0
88 #define PLL_POST_DIV_ENABLE_MASK BIT(5)
89 #define PLL_POST_DIV_ENABLE BIT(5)
90 #define PLL_POST_DIV_DISABLE 0
91 #define DATA_LANE_VOD_RANGE_SET_MASK GENMASK(3, 0)
92 #define DATA_LANE_VOD_RANGE_SET(x) UPDATE(x, 3, 0)
93 #define SAMPLE_CLOCK_DIRECTION_MASK BIT(4)
94 #define SAMPLE_CLOCK_DIRECTION_REVERSE BIT(4)
95 #define SAMPLE_CLOCK_DIRECTION_FORWARD 0
96 #define LOWFRE_EN_MASK BIT(5)
97 #define PLL_OUTPUT_FREQUENCY_DIV_BY_1 0
98 #define PLL_OUTPUT_FREQUENCY_DIV_BY_2 1
99 /* Analog Register Part: reg0b */
100 #define CLOCK_LANE_VOD_RANGE_SET_MASK GENMASK(3, 0)
101 #define CLOCK_LANE_VOD_RANGE_SET(x) UPDATE(x, 3, 0)
102 #define VOD_MIN_RANGE 0x1
103 #define VOD_MID_RANGE 0x3
104 #define VOD_BIG_RANGE 0x7
105 #define VOD_MAX_RANGE 0xf
106 /* Analog Register Part: reg1e */
107 #define PLL_MODE_SEL_MASK GENMASK(6, 5)
108 #define PLL_MODE_SEL_LVDS_MODE 0
109 #define PLL_MODE_SEL_MIPI_MODE BIT(5)
110
111 /* Digital Register Part: reg00 */
112 #define REG_DIG_RSTN_MASK BIT(0)
113 #define REG_DIG_RSTN_NORMAL BIT(0)
114 #define REG_DIG_RSTN_RESET 0
115 /* Digital Register Part: reg01 */
116 #define INVERT_TXCLKESC_MASK BIT(1)
117 #define INVERT_TXCLKESC_ENABLE BIT(1)
118 #define INVERT_TXCLKESC_DISABLE 0
119 #define INVERT_TXBYTECLKHS_MASK BIT(0)
120 #define INVERT_TXBYTECLKHS_ENABLE BIT(0)
121 #define INVERT_TXBYTECLKHS_DISABLE 0
122 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg05 */
123 #define T_LPX_CNT_MASK GENMASK(5, 0)
124 #define T_LPX_CNT(x) UPDATE(x, 5, 0)
125 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg06 */
126 #define T_HS_ZERO_CNT_HI_MASK BIT(7)
127 #define T_HS_ZERO_CNT_HI(x) UPDATE(x, 7, 7)
128 #define T_HS_PREPARE_CNT_MASK GENMASK(6, 0)
129 #define T_HS_PREPARE_CNT(x) UPDATE(x, 6, 0)
130 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg07 */
131 #define T_HS_ZERO_CNT_LO_MASK GENMASK(5, 0)
132 #define T_HS_ZERO_CNT_LO(x) UPDATE(x, 5, 0)
133 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg08 */
134 #define T_HS_TRAIL_CNT_MASK GENMASK(6, 0)
135 #define T_HS_TRAIL_CNT(x) UPDATE(x, 6, 0)
136 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg09 */
137 #define T_HS_EXIT_CNT_LO_MASK GENMASK(4, 0)
138 #define T_HS_EXIT_CNT_LO(x) UPDATE(x, 4, 0)
139 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0a */
140 #define T_CLK_POST_CNT_LO_MASK GENMASK(3, 0)
141 #define T_CLK_POST_CNT_LO(x) UPDATE(x, 3, 0)
142 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0c */
143 #define LPDT_TX_PPI_SYNC_MASK BIT(2)
144 #define LPDT_TX_PPI_SYNC_ENABLE BIT(2)
145 #define LPDT_TX_PPI_SYNC_DISABLE 0
146 #define T_WAKEUP_CNT_HI_MASK GENMASK(1, 0)
147 #define T_WAKEUP_CNT_HI(x) UPDATE(x, 1, 0)
148 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0d */
149 #define T_WAKEUP_CNT_LO_MASK GENMASK(7, 0)
150 #define T_WAKEUP_CNT_LO(x) UPDATE(x, 7, 0)
151 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0e */
152 #define T_CLK_PRE_CNT_MASK GENMASK(3, 0)
153 #define T_CLK_PRE_CNT(x) UPDATE(x, 3, 0)
154 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg10 */
155 #define T_CLK_POST_HI_MASK GENMASK(7, 6)
156 #define T_CLK_POST_HI(x) UPDATE(x, 7, 6)
157 #define T_TA_GO_CNT_MASK GENMASK(5, 0)
158 #define T_TA_GO_CNT(x) UPDATE(x, 5, 0)
159 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg11 */
160 #define T_HS_EXIT_CNT_HI_MASK BIT(6)
161 #define T_HS_EXIT_CNT_HI(x) UPDATE(x, 6, 6)
162 #define T_TA_SURE_CNT_MASK GENMASK(5, 0)
163 #define T_TA_SURE_CNT(x) UPDATE(x, 5, 0)
164 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg12 */
165 #define T_TA_WAIT_CNT_MASK GENMASK(5, 0)
166 #define T_TA_WAIT_CNT(x) UPDATE(x, 5, 0)
167 /* LVDS Register Part: reg00 */
168 #define LVDS_DIGITAL_INTERNAL_RESET_MASK BIT(2)
169 #define LVDS_DIGITAL_INTERNAL_RESET_DISABLE BIT(2)
170 #define LVDS_DIGITAL_INTERNAL_RESET_ENABLE 0
171 /* LVDS Register Part: reg01 */
172 #define LVDS_DIGITAL_INTERNAL_ENABLE_MASK BIT(7)
173 #define LVDS_DIGITAL_INTERNAL_ENABLE BIT(7)
174 #define LVDS_DIGITAL_INTERNAL_DISABLE 0
175 /* LVDS Register Part: reg03 */
176 #define MODE_ENABLE_MASK GENMASK(2, 0)
177 #define TTL_MODE_ENABLE BIT(2)
178 #define LVDS_MODE_ENABLE BIT(1)
179 #define MIPI_MODE_ENABLE BIT(0)
180 /* LVDS Register Part: reg0b */
181 #define LVDS_LANE_EN_MASK GENMASK(7, 3)
182 #define LVDS_DATA_LANE0_EN BIT(7)
183 #define LVDS_DATA_LANE1_EN BIT(6)
184 #define LVDS_DATA_LANE2_EN BIT(5)
185 #define LVDS_DATA_LANE3_EN BIT(4)
186 #define LVDS_CLK_LANE_EN BIT(3)
187 #define LVDS_PLL_POWER_MASK BIT(2)
188 #define LVDS_PLL_POWER_OFF BIT(2)
189 #define LVDS_PLL_POWER_ON 0
190 #define LVDS_BANDGAP_POWER_MASK BIT(0)
191 #define LVDS_BANDGAP_POWER_DOWN BIT(0)
192 #define LVDS_BANDGAP_POWER_ON 0
193
194 #define DSI_PHY_RSTZ 0xa0
195 #define PHY_ENABLECLK BIT(2)
196 #define DSI_PHY_STATUS 0xb0
197 #define PHY_LOCK BIT(0)
198
199 enum soc_type {
200 PX30_VIDEO_PHY,
201 PX30S_VIDEO_PHY,
202 RK3128_VIDEO_PHY,
203 RK3368_VIDEO_PHY,
204 RK3568_VIDEO_PHY,
205 };
206
207 enum phy_max_rate {
208 MAX_1GHZ,
209 MAX_2_5GHZ,
210 };
211
212 struct inno_video_mipi_dphy_timing {
213 unsigned int max_lane_mbps;
214 u8 lpx;
215 u8 hs_prepare;
216 u8 clk_lane_hs_zero;
217 u8 data_lane_hs_zero;
218 u8 hs_trail;
219 };
220
221 struct inno_video_mipi_dphy_info {
222 const struct inno_video_mipi_dphy_timing *inno_mipi_dphy_timing_table;
223 const unsigned int num_timings;
224 enum phy_max_rate phy_max_rate;
225 };
226
227 static const
228 struct inno_video_mipi_dphy_timing inno_mipi_dphy_timing_table_max_1GHz[] = {
229 { 110, 0x0, 0x20, 0x16, 0x02, 0x22},
230 { 150, 0x0, 0x06, 0x16, 0x03, 0x45},
231 { 200, 0x0, 0x18, 0x17, 0x04, 0x0b},
232 { 250, 0x0, 0x05, 0x17, 0x05, 0x16},
233 { 300, 0x0, 0x51, 0x18, 0x06, 0x2c},
234 { 400, 0x0, 0x64, 0x19, 0x07, 0x33},
235 { 500, 0x0, 0x20, 0x1b, 0x07, 0x4e},
236 { 600, 0x0, 0x6a, 0x1d, 0x08, 0x3a},
237 { 700, 0x0, 0x3e, 0x1e, 0x08, 0x6a},
238 { 800, 0x0, 0x21, 0x1f, 0x09, 0x29},
239 {1000, 0x0, 0x09, 0x20, 0x09, 0x27},
240 };
241
242 static const
243 struct inno_video_mipi_dphy_timing inno_mipi_dphy_timing_table_max_2_5GHz[] = {
244 { 110, 0x02, 0x7f, 0x16, 0x02, 0x02},
245 { 150, 0x02, 0x7f, 0x16, 0x03, 0x02},
246 { 200, 0x02, 0x7f, 0x17, 0x04, 0x02},
247 { 250, 0x02, 0x7f, 0x17, 0x05, 0x04},
248 { 300, 0x02, 0x7f, 0x18, 0x06, 0x04},
249 { 400, 0x03, 0x7e, 0x19, 0x07, 0x04},
250 { 500, 0x03, 0x7c, 0x1b, 0x07, 0x08},
251 { 600, 0x03, 0x70, 0x1d, 0x08, 0x10},
252 { 700, 0x05, 0x40, 0x1e, 0x08, 0x30},
253 { 800, 0x05, 0x02, 0x1f, 0x09, 0x30},
254 {1000, 0x05, 0x08, 0x20, 0x09, 0x30},
255 {1200, 0x06, 0x03, 0x32, 0x14, 0x0f},
256 {1400, 0x09, 0x03, 0x32, 0x14, 0x0f},
257 {1600, 0x0d, 0x42, 0x36, 0x0e, 0x0f},
258 {1800, 0x0e, 0x47, 0x7a, 0x0e, 0x0f},
259 {2000, 0x11, 0x64, 0x7a, 0x0e, 0x0b},
260 {2200, 0x13, 0x64, 0x7e, 0x15, 0x0b},
261 {2400, 0x13, 0x33, 0x7f, 0x15, 0x6a},
262 {2500, 0x15, 0x54, 0x7f, 0x15, 0x6a},
263 };
264
265 const struct inno_video_mipi_dphy_info inno_video_mipi_dphy_max_1GHz = {
266 .inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_1GHz,
267 .num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_1GHz),
268 .phy_max_rate = MAX_1GHZ,
269 };
270
271 const struct inno_video_mipi_dphy_info inno_video_mipi_dphy_max_2_5GHz = {
272 .inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_2_5GHz,
273 .num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_2_5GHz),
274 .phy_max_rate = MAX_2_5GHZ,
275 };
276
277 struct mipi_dphy_timing {
278 unsigned int clkmiss;
279 unsigned int clkpost;
280 unsigned int clkpre;
281 unsigned int clkprepare;
282 unsigned int clksettle;
283 unsigned int clktermen;
284 unsigned int clktrail;
285 unsigned int clkzero;
286 unsigned int dtermen;
287 unsigned int eot;
288 unsigned int hsexit;
289 unsigned int hsprepare;
290 unsigned int hszero;
291 unsigned int hssettle;
292 unsigned int hsskip;
293 unsigned int hstrail;
294 unsigned int init;
295 unsigned int lpx;
296 unsigned int taget;
297 unsigned int tago;
298 unsigned int tasure;
299 unsigned int wakeup;
300 };
301
302 struct inno_video_phy {
303 struct udevice *dev;
304 enum phy_mode mode;
305 const struct inno_video_mipi_dphy_info *mipi_dphy_info;
306 struct resource phy;
307 struct resource host;
308 int lanes;
309 struct {
310 u8 prediv;
311 u16 fbdiv;
312 unsigned long rate;
313 } pll;
314 };
315
316 enum {
317 REGISTER_PART_ANALOG,
318 REGISTER_PART_DIGITAL,
319 REGISTER_PART_CLOCK_LANE,
320 REGISTER_PART_DATA0_LANE,
321 REGISTER_PART_DATA1_LANE,
322 REGISTER_PART_DATA2_LANE,
323 REGISTER_PART_DATA3_LANE,
324 REGISTER_PART_LVDS,
325 };
326
phy_update_bits(struct inno_video_phy * inno,u8 first,u8 second,u8 mask,u8 val)327 static inline void phy_update_bits(struct inno_video_phy *inno,
328 u8 first, u8 second, u8 mask, u8 val)
329 {
330 u32 reg = PHY_REG(first, second) << 2;
331 u32 tmp, orig;
332
333 orig = readl(inno->phy.start + reg);
334 tmp = orig & ~mask;
335 tmp |= val & mask;
336 writel(tmp, inno->phy.start + reg);
337 }
338
host_update_bits(struct inno_video_phy * inno,u32 reg,u32 mask,u32 val)339 static inline void host_update_bits(struct inno_video_phy *inno,
340 u32 reg, u32 mask, u32 val)
341 {
342 u32 tmp, orig;
343
344 orig = readl(inno->host.start + reg);
345 tmp = orig & ~mask;
346 tmp |= val & mask;
347 writel(tmp, inno->host.start + reg);
348 }
349
mipi_dphy_timing_get_default(struct mipi_dphy_timing * timing,unsigned long period)350 static void mipi_dphy_timing_get_default(struct mipi_dphy_timing *timing,
351 unsigned long period)
352 {
353 /* Global Operation Timing Parameters */
354 timing->clkmiss = 0;
355 timing->clkpost = 70000 + 52 * period;
356 timing->clkpre = 8 * period;
357 timing->clkprepare = 65000;
358 timing->clksettle = 95000;
359 timing->clktermen = 0;
360 timing->clktrail = 80000;
361 timing->clkzero = 260000;
362 timing->dtermen = 0;
363 timing->eot = 0;
364 timing->hsexit = 120000;
365 timing->hsprepare = 65000 + 4 * period;
366 timing->hszero = 145000 + 6 * period;
367 timing->hssettle = 85000 + 6 * period;
368 timing->hsskip = 40000;
369 timing->hstrail = max(8 * period, 60000 + 4 * period);
370 timing->init = 100000000;
371 timing->lpx = 60000;
372 timing->taget = 5 * timing->lpx;
373 timing->tago = 4 * timing->lpx;
374 timing->tasure = 2 * timing->lpx;
375 timing->wakeup = 1000000000;
376 }
377
378 static const struct inno_video_mipi_dphy_timing *
inno_mipi_dphy_get_timing(struct inno_video_phy * inno)379 inno_mipi_dphy_get_timing(struct inno_video_phy *inno)
380 {
381 const struct inno_video_mipi_dphy_timing *timings;
382 unsigned int num_timings;
383 unsigned int lane_mbps = inno->pll.rate / USEC_PER_SEC;
384 unsigned int i;
385
386 timings = inno->mipi_dphy_info->inno_mipi_dphy_timing_table;
387 num_timings = inno->mipi_dphy_info->num_timings;
388
389 for (i = 0; i < num_timings; i++)
390 if (lane_mbps <= timings[i].max_lane_mbps)
391 break;
392
393 if (i == num_timings)
394 --i;
395
396 return &timings[i];
397 }
398
inno_mipi_dphy_max_2_5GHz_pll_enable(struct inno_video_phy * inno)399 static void inno_mipi_dphy_max_2_5GHz_pll_enable(struct inno_video_phy *inno)
400 {
401 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
402 REG_PREDIV_MASK, REG_PREDIV(inno->pll.prediv));
403 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
404 REG_FBDIV_HI_MASK, REG_FBDIV_HI(inno->pll.fbdiv >> 8));
405 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x04,
406 REG_FBDIV_LO_MASK, REG_FBDIV_LO(inno->pll.fbdiv));
407 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x08,
408 PLL_POST_DIV_ENABLE_MASK, PLL_POST_DIV_ENABLE);
409 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x0b,
410 CLOCK_LANE_VOD_RANGE_SET_MASK,
411 CLOCK_LANE_VOD_RANGE_SET(VOD_MAX_RANGE));
412 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
413 REG_LDOPD_MASK | REG_PLLPD_MASK,
414 REG_LDOPD_POWER_ON | REG_PLLPD_POWER_ON);
415 }
416
inno_mipi_dphy_max_1GHz_pll_enable(struct inno_video_phy * inno)417 static void inno_mipi_dphy_max_1GHz_pll_enable(struct inno_video_phy *inno)
418 {
419 /* Configure PLL */
420 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
421 REG_PREDIV_MASK, REG_PREDIV(inno->pll.prediv));
422 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
423 REG_FBDIV_HI_MASK, REG_FBDIV_HI(inno->pll.fbdiv >> 8));
424 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x04,
425 REG_FBDIV_LO_MASK, REG_FBDIV_LO(inno->pll.fbdiv));
426 /* Enable PLL and LDO */
427 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
428 REG_LDOPD_MASK | REG_PLLPD_MASK,
429 REG_LDOPD_POWER_ON | REG_PLLPD_POWER_ON);
430 }
431
inno_mipi_dphy_reset(struct inno_video_phy * inno)432 static void inno_mipi_dphy_reset(struct inno_video_phy *inno)
433 {
434 /* Reset analog */
435 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
436 REG_SYNCRST_MASK, REG_SYNCRST_RESET);
437 udelay(1);
438 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
439 REG_SYNCRST_MASK, REG_SYNCRST_NORMAL);
440 /* Reset digital */
441 phy_update_bits(inno, REGISTER_PART_DIGITAL, 0x00,
442 REG_DIG_RSTN_MASK, REG_DIG_RSTN_RESET);
443 udelay(1);
444 phy_update_bits(inno, REGISTER_PART_DIGITAL, 0x00,
445 REG_DIG_RSTN_MASK, REG_DIG_RSTN_NORMAL);
446 }
447
inno_mipi_dphy_timing_init(struct inno_video_phy * inno)448 static void inno_mipi_dphy_timing_init(struct inno_video_phy *inno)
449 {
450 struct mipi_dphy_timing gotp;
451 u32 t_txbyteclkhs, t_txclkesc, ui;
452 u32 txbyteclkhs, txclkesc, esc_clk_div;
453 u32 hs_exit, clk_post, clk_pre, wakeup, lpx, ta_go, ta_sure, ta_wait;
454 u32 hs_prepare, hs_trail, hs_zero, clk_lane_hs_zero, data_lane_hs_zero;
455 const struct inno_video_mipi_dphy_timing *timing;
456 unsigned int i;
457
458 txbyteclkhs = inno->pll.rate / 8;
459 t_txbyteclkhs = div_u64(PSEC_PER_SEC, txbyteclkhs);
460 esc_clk_div = DIV_ROUND_UP(txbyteclkhs, 20000000);
461 txclkesc = txbyteclkhs / esc_clk_div;
462 t_txclkesc = div_u64(PSEC_PER_SEC, txclkesc);
463
464 ui = div_u64(PSEC_PER_SEC, inno->pll.rate);
465
466 memset(&gotp, 0, sizeof(gotp));
467 mipi_dphy_timing_get_default(&gotp, ui);
468
469 /*
470 * The value of counter for HS Ths-exit
471 * Ths-exit = Tpin_txbyteclkhs * value
472 */
473 hs_exit = DIV_ROUND_UP(gotp.hsexit, t_txbyteclkhs);
474 /*
475 * The value of counter for HS Tclk-post
476 * Tclk-post = Tpin_txbyteclkhs * value
477 */
478 clk_post = DIV_ROUND_UP(gotp.clkpost, t_txbyteclkhs);
479 /*
480 * The value of counter for HS Tclk-pre
481 * Tclk-pre = Tpin_txbyteclkhs * value
482 */
483 clk_pre = DIV_ROUND_UP(gotp.clkpre, t_txbyteclkhs);
484
485 /*
486 * The value of counter for HS Tlpx Time
487 * Tlpx = Tpin_txbyteclkhs * (2 + value)
488 */
489 lpx = DIV_ROUND_UP(gotp.lpx, t_txbyteclkhs);
490 if (lpx >= 2)
491 lpx -= 2;
492
493 /*
494 * The value of counter for HS Tta-go
495 * Tta-go for turnaround
496 * Tta-go = Ttxclkesc * value
497 */
498 ta_go = DIV_ROUND_UP(gotp.tago, t_txclkesc);
499 /*
500 * The value of counter for HS Tta-sure
501 * Tta-sure for turnaround
502 * Tta-sure = Ttxclkesc * value
503 */
504 ta_sure = DIV_ROUND_UP(gotp.tasure, t_txclkesc);
505 /*
506 * The value of counter for HS Tta-wait
507 * Tta-wait for turnaround
508 * Tta-wait = Ttxclkesc * value
509 */
510 ta_wait = DIV_ROUND_UP(gotp.taget, t_txclkesc);
511
512 timing = inno_mipi_dphy_get_timing(inno);
513
514 /*
515 * The value of counter for HS Tlpx Time
516 * Tlpx = Tpin_txbyteclkhs * (2 + value)
517 */
518 if (inno->mipi_dphy_info->phy_max_rate == MAX_1GHZ) {
519 lpx = DIV_ROUND_UP(gotp.lpx, t_txbyteclkhs);
520 if (lpx >= 2)
521 lpx -= 2;
522 } else {
523 lpx = timing->lpx;
524 }
525
526 hs_prepare = timing->hs_prepare;
527 hs_trail = timing->hs_trail;
528 clk_lane_hs_zero = timing->clk_lane_hs_zero;
529 data_lane_hs_zero = timing->data_lane_hs_zero;
530 wakeup = 0x3ff;
531
532 for (i = REGISTER_PART_CLOCK_LANE; i <= REGISTER_PART_DATA3_LANE; i++) {
533 if (i == REGISTER_PART_CLOCK_LANE)
534 hs_zero = clk_lane_hs_zero;
535 else
536 hs_zero = data_lane_hs_zero;
537
538 phy_update_bits(inno, i, 0x05, T_LPX_CNT_MASK,
539 T_LPX_CNT(lpx));
540 phy_update_bits(inno, i, 0x06, T_HS_PREPARE_CNT_MASK,
541 T_HS_PREPARE_CNT(hs_prepare));
542
543 if (inno->mipi_dphy_info->phy_max_rate == MAX_2_5GHZ)
544 phy_update_bits(inno, i, 0x06, T_HS_ZERO_CNT_HI_MASK,
545 T_HS_ZERO_CNT_HI(hs_zero >> 6));
546
547 phy_update_bits(inno, i, 0x07, T_HS_ZERO_CNT_LO_MASK,
548 T_HS_ZERO_CNT_LO(hs_zero));
549 phy_update_bits(inno, i, 0x08, T_HS_TRAIL_CNT_MASK,
550 T_HS_TRAIL_CNT(hs_trail));
551
552 if (inno->mipi_dphy_info->phy_max_rate == MAX_2_5GHZ)
553 phy_update_bits(inno, i, 0x11, T_HS_EXIT_CNT_HI_MASK,
554 T_HS_EXIT_CNT_HI(hs_exit >> 5));
555
556 phy_update_bits(inno, i, 0x09, T_HS_EXIT_CNT_LO_MASK,
557 T_HS_EXIT_CNT_LO(hs_exit));
558
559 if (inno->mipi_dphy_info->phy_max_rate == MAX_2_5GHZ)
560 phy_update_bits(inno, i, 0x10, T_CLK_POST_HI_MASK,
561 T_CLK_POST_HI(clk_post >> 4));
562
563 phy_update_bits(inno, i, 0x0a, T_CLK_POST_CNT_LO_MASK,
564 T_CLK_POST_CNT_LO(clk_post));
565 phy_update_bits(inno, i, 0x0e, T_CLK_PRE_CNT_MASK,
566 T_CLK_PRE_CNT(clk_pre));
567 phy_update_bits(inno, i, 0x0c, T_WAKEUP_CNT_HI_MASK,
568 T_WAKEUP_CNT_HI(wakeup >> 8));
569 phy_update_bits(inno, i, 0x0d, T_WAKEUP_CNT_LO_MASK,
570 T_WAKEUP_CNT_LO(wakeup));
571 phy_update_bits(inno, i, 0x10, T_TA_GO_CNT_MASK,
572 T_TA_GO_CNT(ta_go));
573 phy_update_bits(inno, i, 0x11, T_TA_SURE_CNT_MASK,
574 T_TA_SURE_CNT(ta_sure));
575 phy_update_bits(inno, i, 0x12, T_TA_WAIT_CNT_MASK,
576 T_TA_WAIT_CNT(ta_wait));
577 }
578 }
579
inno_mipi_dphy_lane_enable(struct inno_video_phy * inno)580 static void inno_mipi_dphy_lane_enable(struct inno_video_phy *inno)
581 {
582 u8 val = LANE_EN_CK;
583
584 switch (inno->lanes) {
585 case 1:
586 val |= LANE_EN_0;
587 break;
588 case 2:
589 val |= LANE_EN_1 | LANE_EN_0;
590 break;
591 case 3:
592 val |= LANE_EN_2 | LANE_EN_1 | LANE_EN_0;
593 break;
594 case 4:
595 default:
596 val |= LANE_EN_3 | LANE_EN_2 | LANE_EN_1 | LANE_EN_0;
597 break;
598 }
599
600 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, LANE_EN_MASK, val);
601 }
602
inno_video_phy_mipi_mode_enable(struct inno_video_phy * inno)603 static void inno_video_phy_mipi_mode_enable(struct inno_video_phy *inno)
604 {
605 struct rockchip_phy *phy =
606 (struct rockchip_phy *)dev_get_driver_data(inno->dev);
607
608 /* Select MIPI mode */
609 phy_update_bits(inno, REGISTER_PART_LVDS, 0x03,
610 MODE_ENABLE_MASK, MIPI_MODE_ENABLE);
611
612 /* set px30 pin_txclkesc_0 invert disable */
613 if (phy->soc_type == PX30_VIDEO_PHY || phy->soc_type == PX30S_VIDEO_PHY)
614 phy_update_bits(inno, REGISTER_PART_DIGITAL, 0x01,
615 INVERT_TXCLKESC_MASK, INVERT_TXCLKESC_DISABLE);
616
617 if (inno->mipi_dphy_info->phy_max_rate == MAX_2_5GHZ)
618 inno_mipi_dphy_max_2_5GHz_pll_enable(inno);
619 else
620 inno_mipi_dphy_max_1GHz_pll_enable(inno);
621
622 inno_mipi_dphy_reset(inno);
623 inno_mipi_dphy_timing_init(inno);
624 inno_mipi_dphy_lane_enable(inno);
625 }
626
inno_video_phy_lvds_mode_enable(struct inno_video_phy * inno)627 static void inno_video_phy_lvds_mode_enable(struct inno_video_phy *inno)
628 {
629 u8 prediv = 2;
630 u16 fbdiv = 28;
631 u32 val;
632 int ret;
633
634 /* Sample clock reverse direction */
635 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x08,
636 SAMPLE_CLOCK_DIRECTION_MASK | LOWFRE_EN_MASK,
637 SAMPLE_CLOCK_DIRECTION_REVERSE |
638 PLL_OUTPUT_FREQUENCY_DIV_BY_1);
639
640 /* Reset LVDS digital logic */
641 phy_update_bits(inno, REGISTER_PART_LVDS, 0x00,
642 LVDS_DIGITAL_INTERNAL_RESET_MASK,
643 LVDS_DIGITAL_INTERNAL_RESET_ENABLE);
644 phy_update_bits(inno, REGISTER_PART_LVDS, 0x00,
645 LVDS_DIGITAL_INTERNAL_RESET_MASK,
646 LVDS_DIGITAL_INTERNAL_RESET_DISABLE);
647
648 /* Select LVDS mode */
649 phy_update_bits(inno, REGISTER_PART_LVDS, 0x03,
650 MODE_ENABLE_MASK, LVDS_MODE_ENABLE);
651
652 /* Configure PLL */
653 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
654 REG_PREDIV_MASK, REG_PREDIV(prediv));
655 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
656 REG_FBDIV_HI_MASK, REG_FBDIV_HI(fbdiv >> 8));
657 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x04,
658 REG_FBDIV_LO_MASK, REG_FBDIV_LO(fbdiv));
659 phy_update_bits(inno, REGISTER_PART_LVDS, 0x08, 0xff, 0xfc);
660
661 /* Enable PLL and Bandgap */
662 phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b,
663 LVDS_PLL_POWER_MASK | LVDS_BANDGAP_POWER_MASK,
664 LVDS_PLL_POWER_ON | LVDS_BANDGAP_POWER_ON);
665
666 ret = readl_poll_timeout(inno->host.start + DSI_PHY_STATUS,
667 val, val & PHY_LOCK, 10000);
668 if (ret)
669 dev_err(phy->dev, "PLL is not lock\n");
670
671 /* Select PLL mode */
672 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x1e,
673 PLL_MODE_SEL_MASK, PLL_MODE_SEL_LVDS_MODE);
674
675 /* Enable LVDS digital logic */
676 phy_update_bits(inno, REGISTER_PART_LVDS, 0x01,
677 LVDS_DIGITAL_INTERNAL_ENABLE_MASK,
678 LVDS_DIGITAL_INTERNAL_ENABLE);
679 /* Enable LVDS analog driver */
680 phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b,
681 LVDS_LANE_EN_MASK, LVDS_CLK_LANE_EN |
682 LVDS_DATA_LANE0_EN | LVDS_DATA_LANE1_EN |
683 LVDS_DATA_LANE2_EN | LVDS_DATA_LANE3_EN);
684 }
685
inno_video_phy_ttl_mode_enable(struct inno_video_phy * inno)686 static void inno_video_phy_ttl_mode_enable(struct inno_video_phy *inno)
687 {
688 /* Reset digital logic */
689 phy_update_bits(inno, REGISTER_PART_LVDS, 0x00,
690 LVDS_DIGITAL_INTERNAL_RESET_MASK,
691 LVDS_DIGITAL_INTERNAL_RESET_ENABLE);
692 phy_update_bits(inno, REGISTER_PART_LVDS, 0x00,
693 LVDS_DIGITAL_INTERNAL_RESET_MASK,
694 LVDS_DIGITAL_INTERNAL_RESET_DISABLE);
695
696 /* Select TTL mode */
697 phy_update_bits(inno, REGISTER_PART_LVDS, 0x03,
698 MODE_ENABLE_MASK, TTL_MODE_ENABLE);
699 /* Enable digital logic */
700 phy_update_bits(inno, REGISTER_PART_LVDS, 0x01,
701 LVDS_DIGITAL_INTERNAL_ENABLE_MASK,
702 LVDS_DIGITAL_INTERNAL_ENABLE);
703 /* Enable analog driver */
704 phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b,
705 LVDS_LANE_EN_MASK, LVDS_CLK_LANE_EN |
706 LVDS_DATA_LANE0_EN | LVDS_DATA_LANE1_EN |
707 LVDS_DATA_LANE2_EN | LVDS_DATA_LANE3_EN);
708 /* Enable for clk lane in TTL mode */
709 host_update_bits(inno, DSI_PHY_RSTZ, PHY_ENABLECLK, PHY_ENABLECLK);
710 }
711
inno_video_phy_power_on(struct rockchip_phy * phy)712 static int inno_video_phy_power_on(struct rockchip_phy *phy)
713 {
714 struct inno_video_phy *inno = dev_get_priv(phy->dev);
715
716 /* Bandgap power on */
717 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
718 BANDGAP_POWER_MASK, BANDGAP_POWER_ON);
719 /* Enable power work */
720 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
721 POWER_WORK_MASK, POWER_WORK_ENABLE);
722
723 switch (inno->mode) {
724 case PHY_MODE_MIPI_DPHY:
725 inno_video_phy_mipi_mode_enable(inno);
726 break;
727 case PHY_MODE_VIDEO_LVDS:
728 inno_video_phy_lvds_mode_enable(inno);
729 break;
730 case PHY_MODE_VIDEO_TTL:
731 inno_video_phy_ttl_mode_enable(inno);
732 break;
733 default:
734 return -EINVAL;
735 }
736
737 return 0;
738 }
739
inno_video_phy_power_off(struct rockchip_phy * phy)740 static int inno_video_phy_power_off(struct rockchip_phy *phy)
741 {
742 struct inno_video_phy *inno = dev_get_priv(phy->dev);
743
744 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, LANE_EN_MASK, 0);
745 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
746 REG_LDOPD_MASK | REG_PLLPD_MASK,
747 REG_LDOPD_POWER_DOWN | REG_PLLPD_POWER_DOWN);
748 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
749 POWER_WORK_MASK, POWER_WORK_DISABLE);
750 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
751 BANDGAP_POWER_MASK, BANDGAP_POWER_DOWN);
752
753 phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b, LVDS_LANE_EN_MASK, 0);
754 phy_update_bits(inno, REGISTER_PART_LVDS, 0x01,
755 LVDS_DIGITAL_INTERNAL_ENABLE_MASK,
756 LVDS_DIGITAL_INTERNAL_DISABLE);
757 phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b,
758 LVDS_PLL_POWER_MASK | LVDS_BANDGAP_POWER_MASK,
759 LVDS_PLL_POWER_OFF | LVDS_BANDGAP_POWER_DOWN);
760
761 return 0;
762 }
763
inno_video_phy_pll_round_rate(unsigned long prate,unsigned long rate,u8 * prediv,u16 * fbdiv)764 static unsigned long inno_video_phy_pll_round_rate(unsigned long prate,
765 unsigned long rate,
766 u8 *prediv, u16 *fbdiv)
767 {
768 unsigned long best_freq = 0;
769 unsigned long fref, fout;
770 u8 min_prediv, max_prediv;
771 u8 _prediv, best_prediv = 1;
772 u16 _fbdiv, best_fbdiv = 1;
773 u32 min_delta = 0xffffffff;
774
775 /*
776 * The PLL output frequency can be calculated using a simple formula:
777 * PLL_Output_Frequency = (FREF / PREDIV * FBDIV) / 2
778 * PLL_Output_Frequency: it is equal to DDR-Clock-Frequency * 2
779 */
780 fref = prate / 2;
781 if (rate > 1000000000UL)
782 fout = 1000000000UL;
783 else
784 fout = rate;
785
786 /* 5Mhz < Fref / prediv < 40MHz */
787 min_prediv = DIV_ROUND_UP(fref, 40000000);
788 max_prediv = fref / 5000000;
789
790 for (_prediv = min_prediv; _prediv <= max_prediv; _prediv++) {
791 u64 tmp;
792 u32 delta;
793
794 tmp = (u64)fout * _prediv;
795 do_div(tmp, fref);
796 _fbdiv = tmp;
797
798 /*
799 * The all possible settings of feedback divider are
800 * 12, 13, 14, 16, ~ 511
801 */
802 if (_fbdiv == 15)
803 continue;
804
805 if (_fbdiv < 12 || _fbdiv > 511)
806 continue;
807
808 tmp = (u64)_fbdiv * fref;
809 do_div(tmp, _prediv);
810
811 delta = abs(fout - tmp);
812 if (!delta) {
813 best_prediv = _prediv;
814 best_fbdiv = _fbdiv;
815 best_freq = tmp;
816 break;
817 } else if (delta < min_delta) {
818 best_prediv = _prediv;
819 best_fbdiv = _fbdiv;
820 best_freq = tmp;
821 min_delta = delta;
822 }
823 }
824
825 if (best_freq) {
826 *prediv = best_prediv;
827 *fbdiv = best_fbdiv;
828 }
829
830 return best_freq;
831 }
832
inno_video_phy_set_pll(struct rockchip_phy * phy,unsigned long rate)833 static unsigned long inno_video_phy_set_pll(struct rockchip_phy *phy,
834 unsigned long rate)
835 {
836 struct inno_video_phy *inno = dev_get_priv(phy->dev);
837 unsigned long fin, fout;
838 u16 fbdiv = 1;
839 u8 prediv = 1;
840
841 fin = 24000000;
842 fout = inno_video_phy_pll_round_rate(fin, rate, &prediv, &fbdiv);
843
844 dev_dbg(phy->dev, "fin=%lu, fout=%lu, prediv=%u, fbdiv=%u\n",
845 fin, fout, prediv, fbdiv);
846
847 inno->pll.prediv = prediv;
848 inno->pll.fbdiv = fbdiv;
849 inno->pll.rate = fout;
850
851 return fout;
852 }
853
inno_video_phy_set_mode(struct rockchip_phy * phy,enum phy_mode mode)854 static int inno_video_phy_set_mode(struct rockchip_phy *phy,
855 enum phy_mode mode)
856 {
857 struct inno_video_phy *inno = dev_get_priv(phy->dev);
858
859 switch (mode) {
860 case PHY_MODE_MIPI_DPHY:
861 case PHY_MODE_VIDEO_LVDS:
862 case PHY_MODE_VIDEO_TTL:
863 inno->mode = mode;
864 break;
865 default:
866 return -EINVAL;
867 }
868
869 return 0;
870 }
871
inno_video_phy_probe(struct udevice * dev)872 static int inno_video_phy_probe(struct udevice *dev)
873 {
874 struct inno_video_phy *inno = dev_get_priv(dev);
875 struct rockchip_phy *tmp_phy;
876 struct rockchip_phy *phy;
877 int ret;
878
879 phy = calloc(1, sizeof(*phy));
880 if (!phy)
881 return -ENOMEM;
882
883 tmp_phy = (struct rockchip_phy *)dev_get_driver_data(dev);
884 dev->driver_data = (ulong)phy;
885 memcpy(phy, tmp_phy, sizeof(*phy));
886
887 inno->dev = dev;
888 inno->mipi_dphy_info = phy->data;
889 if (soc_is_px30s())
890 inno->mipi_dphy_info = &inno_video_mipi_dphy_max_2_5GHz;
891
892 inno->lanes = ofnode_read_u32_default(dev->node, "inno,lanes", 4);
893
894 ret = dev_read_resource(dev, 0, &inno->phy);
895 if (ret < 0) {
896 dev_err(dev, "resource \"phy\" not found\n");
897 return ret;
898 }
899
900 ret = dev_read_resource(dev, 1, &inno->host);
901 if (ret < 0) {
902 dev_err(dev, "resource \"host\" not found\n");
903 return ret;
904 }
905
906 phy->dev = dev;
907
908 return 0;
909 }
910
911 static const struct rockchip_phy_funcs inno_video_phy_funcs = {
912 .power_on = inno_video_phy_power_on,
913 .power_off = inno_video_phy_power_off,
914 .set_pll = inno_video_phy_set_pll,
915 .set_mode = inno_video_phy_set_mode,
916 };
917
918 static struct rockchip_phy px30_inno_video_phy_driver_data = {
919 .soc_type = PX30_VIDEO_PHY,
920 .funcs = &inno_video_phy_funcs,
921 .data = &inno_video_mipi_dphy_max_1GHz,
922 };
923
924 static struct rockchip_phy px30s_inno_video_phy_driver_data = {
925 .soc_type = PX30S_VIDEO_PHY,
926 .funcs = &inno_video_phy_funcs,
927 .data = &inno_video_mipi_dphy_max_2_5GHz,
928 };
929
930 static struct rockchip_phy rk3128_inno_video_phy_driver_data = {
931 .soc_type = RK3128_VIDEO_PHY,
932 .funcs = &inno_video_phy_funcs,
933 .data = &inno_video_mipi_dphy_max_1GHz,
934 };
935
936 static struct rockchip_phy rk3368_inno_video_phy_driver_data = {
937 .soc_type = RK3368_VIDEO_PHY,
938 .funcs = &inno_video_phy_funcs,
939 .data = &inno_video_mipi_dphy_max_1GHz,
940 };
941
942 static struct rockchip_phy rk3568_inno_video_phy_driver_data = {
943 .soc_type = RK3568_VIDEO_PHY,
944 .funcs = &inno_video_phy_funcs,
945 .data = &inno_video_mipi_dphy_max_2_5GHz,
946 };
947
948 static const struct udevice_id inno_video_phy_ids[] = {
949 {
950 .compatible = "rockchip,px30-video-phy",
951 .data = (ulong)&px30_inno_video_phy_driver_data,
952 },
953 {
954 .compatible = "rockchip,px30s-video-phy",
955 .data = (ulong)&px30s_inno_video_phy_driver_data,
956 },
957 {
958 .compatible = "rockchip,rk3128-video-phy",
959 .data = (ulong)&rk3128_inno_video_phy_driver_data,
960 },
961 {
962 .compatible = "rockchip,rk3368-video-phy",
963 .data = (ulong)&rk3368_inno_video_phy_driver_data,
964 },
965 {
966 .compatible = "rockchip,rk3568-video-phy",
967 .data = (ulong)&rk3568_inno_video_phy_driver_data,
968 },
969 {}
970 };
971
972 U_BOOT_DRIVER(inno_video_combo_phy) = {
973 .name = "inno_video_combo_phy",
974 .id = UCLASS_PHY,
975 .of_match = inno_video_phy_ids,
976 .probe = inno_video_phy_probe,
977 .priv_auto_alloc_size = sizeof(struct inno_video_phy),
978 };
979