| /rk3399_ARM-atf/plat/renesas/rcar_gen4/ |
| H A D | plat_pm.c | 100 for (unsigned int i = 0U; i < PLATFORM_CORE_COUNT; i++) in rcar_pwr_domain_suspend() local
101 gicv3_rdistif_save(i, &rdist_ctx[i]); in rcar_pwr_domain_suspend()
126 for (unsigned int i = 0U; i < PLATFORM_CORE_COUNT; i++) in rcar_pwr_domain_suspend_finish() local
127 gicv3_rdistif_init_restore(i, &rdist_ctx[i]); in rcar_pwr_domain_suspend_finish()
163 uint64_t i; in rcar_validate_power_state() local
171 for (i = MPIDR_AFFLVL0; i <= (uint64_t)pwr_lvl; i++) in rcar_validate_power_state()
172 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; in rcar_validate_power_state()
183 uint64_t i; in rcar_get_sys_suspend_power_state() local
191 for (i = MPIDR_AFFLVL0; i < (uint64_t)PLAT_MAX_PWR_LVL; i++) in rcar_get_sys_suspend_power_state()
192 req_state->pwr_domain_state[i] = PLAT_MAX_RET_STATE; in rcar_get_sys_suspend_power_state()
[all …]
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| /rk3399_ARM-atf/plat/arm/board/tc/ |
| H A D | tc_bl31_setup.c | 46 for (size_t i = 0U; i < output_size; i++) { in mbedtls_psa_external_get_random() local
47 output[i] = (uint8_t)(read_cntpct_el0() & 0xFFU); in mbedtls_psa_external_get_random()
88 for (int i = 0; i < MCN_INSTANCES; i++) { in enable_ns_mcn_pmu() local
89 uintptr_t mcn_scr = MCN_MICROARCH_BASE_ADDR(i) + in enable_ns_mcn_pmu()
103 for (int i = 0; i < MCN_INSTANCES; i++) { in set_mcn_slc_alloc_mode() local
104 uintptr_t slccfg_ctl_ns = MCN_MPAM_NS_BASE_ADDR(i) + in set_mcn_slc_alloc_mode()
106 uintptr_t slccfg_ctl_s = MCN_MPAM_S_BASE_ADDR(i) + in set_mcn_slc_alloc_mode()
129 for (int i = 0; i < MCN_INSTANCES; i++) { in set_mcn_mtu_tag_addr() local
130 uintptr_t mtu_tag_addr_base_lo = MCN_MTU_BASE_ADDR(i) + in set_mcn_mtu_tag_addr()
132 uintptr_t mtu_tag_addr_base_hi = MCN_MTU_BASE_ADDR(i) + in set_mcn_mtu_tag_addr()
[all …]
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| /rk3399_ARM-atf/drivers/partition/ |
| H A D | partition.c | 28 int i, j, len; in dump_entries() local
31 for (i = 0; i < num; i++) { in dump_entries()
32 len = snprintf(name, EFI_NAMELEN, "%s", list.list[i].name); in dump_entries()
37 VERBOSE("%d: %s %" PRIx64 "-%" PRIx64 "\n", i + 1, name, list.list[i].start, in dump_entries()
38 list.list[i].start + list.list[i].length - 4); in dump_entries()
188 unsigned int i; in load_mbr_entries() local
192 for (i = 0U; i < list.entry_count; i++) { in load_mbr_entries()
193 load_mbr_entry(image_handle, &mbr_entry, i); in load_mbr_entries()
194 list.list[i].start = mbr_entry.first_lba * 512; in load_mbr_entries()
195 list.list[i].length = mbr_entry.sector_nums * 512; in load_mbr_entries()
[all …]
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| H A D | gpt.c | 19 int i; in unicode_to_ascii() local
28 for (i = 1; i < (EFI_NAMELEN << 1); i += 2) { in unicode_to_ascii()
29 if (name[i] != '\0') { in unicode_to_ascii()
34 for (i = 0; i < (EFI_NAMELEN << 1); i += 2) { in unicode_to_ascii()
35 str_out[i >> 1] = name[i]; in unicode_to_ascii()
36 if (name[i] == '\0') { in unicode_to_ascii()
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| /rk3399_ARM-atf/drivers/renesas/rzg/qos/G2E/ |
| H A D | qos_init_g2e_v10.c | 113 uint32_t i; in qos_init_g2e_v10() local
115 for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) { in qos_init_g2e_v10()
116 mmio_write_64(QOSBW_FIX_QOS_BANK0 + i * 8U, mstat_fix[i]); in qos_init_g2e_v10()
117 mmio_write_64(QOSBW_FIX_QOS_BANK1 + i * 8U, mstat_fix[i]); in qos_init_g2e_v10()
119 for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) { in qos_init_g2e_v10()
120 mmio_write_64(QOSBW_BE_QOS_BANK0 + i * 8U, mstat_be[i]); in qos_init_g2e_v10()
121 mmio_write_64(QOSBW_BE_QOS_BANK1 + i * 8U, mstat_be[i]); in qos_init_g2e_v10()
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| /rk3399_ARM-atf/drivers/renesas/rcar/qos/E3/ |
| H A D | qos_init_e3_v10.c | 115 uint32_t i; in qos_init_e3_v10() local
117 for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) { in qos_init_e3_v10()
118 io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]); in qos_init_e3_v10()
119 io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]); in qos_init_e3_v10()
121 for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) { in qos_init_e3_v10()
122 io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]); in qos_init_e3_v10()
123 io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]); in qos_init_e3_v10()
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| /rk3399_ARM-atf/drivers/st/ddr/phy/phyinit/usercustom/ |
| H A D | ddrphy_phyinit_usercustom_custompretrain.c | 48 uint32_t i = 0U; in ddrphy_phyinit_usercustom_custompretrain() local
55 for (i = 0U; i < NB_HWT_SWIZZLE; i++) { in ddrphy_phyinit_usercustom_custompretrain()
56 mmio_write_16(base + (i * sizeof(uint32_t)), in ddrphy_phyinit_usercustom_custompretrain()
57 (uint16_t)config->uis.swizzle[i]); in ddrphy_phyinit_usercustom_custompretrain()
62 for (j = 0U; j < NB_AC_SWIZZLE; j++, i++) { in ddrphy_phyinit_usercustom_custompretrain()
63 mmio_write_32(base + (j * sizeof(uint32_t)), config->uis.swizzle[i]); in ddrphy_phyinit_usercustom_custompretrain()
70 for (j = 0U; j < NB_DQLNSEL_SWIZZLE_PER_BYTE; j++, i++) { in ddrphy_phyinit_usercustom_custompretrain()
72 (uint16_t)config->uis.swizzle[i]); in ddrphy_phyinit_usercustom_custompretrain()
78 for (j = 0U; j < NB_MAPCAATODFI_SWIZZLE; j++, i++) { in ddrphy_phyinit_usercustom_custompretrain()
80 (uint16_t)config->uis.swizzle[i]); in ddrphy_phyinit_usercustom_custompretrain()
[all …]
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| /rk3399_ARM-atf/plat/mediatek/mt8186/drivers/spm/ |
| H A D | mt_spm_cond.c | 104 unsigned int i; in mt_spm_cond_check() local
110 for (i = 0U; i < PLAT_SPM_COND_MAX; i++) { in mt_spm_cond_check()
112 res->table_cg[i] = (src->table_cg[i] & dest->table_cg[i]); in mt_spm_cond_check()
113 if (is_system_suspend && ((res->table_cg[i]) != 0U)) { in mt_spm_cond_check()
115 dest->name, i, idle_cg_info[i].addr, in mt_spm_cond_check()
116 res->table_cg[i]); in mt_spm_cond_check()
119 if ((res->table_cg[i]) != 0U) { in mt_spm_cond_check()
120 blocked |= BIT(i); in mt_spm_cond_check()
122 } else if ((src->table_cg[i] & dest->table_cg[i]) != 0U) { in mt_spm_cond_check()
123 blocked |= BIT(i); in mt_spm_cond_check()
[all …]
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| /rk3399_ARM-atf/plat/mediatek/mt8192/drivers/spm/ |
| H A D | mt_spm_cond.c | 107 unsigned int blocked = 0U, i; in mt_spm_cond_check() local
114 for (i = 0U; i < PLAT_SPM_COND_MAX; i++) { in mt_spm_cond_check()
116 res->table_cg[i] = in mt_spm_cond_check()
117 (src->table_cg[i] & dest->table_cg[i]); in mt_spm_cond_check()
119 if (is_system_suspend && (res->table_cg[i] != 0U)) { in mt_spm_cond_check()
121 dest->name, i, idle_cg_info[i].addr, in mt_spm_cond_check()
122 res->table_cg[i]); in mt_spm_cond_check()
125 if (res->table_cg[i] != 0U) { in mt_spm_cond_check()
126 blocked |= (1U << i); in mt_spm_cond_check()
128 } else if ((src->table_cg[i] & dest->table_cg[i]) != 0U) { in mt_spm_cond_check()
[all …]
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| /rk3399_ARM-atf/plat/rockchip/rk3576/drivers/pmu/ |
| H A D | pmu.c | 321 int i; in clk_gate_con_disable() local
323 for (i = 0; i < CRU_CLKGATE_CON_CNT; i++) { in clk_gate_con_disable()
325 if (i == 16) { in clk_gate_con_disable()
326 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(i), in clk_gate_con_disable()
329 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(i), in clk_gate_con_disable()
334 for (i = 0; i < PHP_CRU_CLKGATE_CON_CNT; i++) in clk_gate_con_disable()
335 mmio_write_32(PHP_CRU_BASE + PHP_CRU_CLKGATE_CON(i), 0xffff0000); in clk_gate_con_disable()
337 for (i = 0; i < SECURE_CRU_CLKGATE_CON_CNT; i++) in clk_gate_con_disable()
338 mmio_write_32(SECURE_CRU_BASE + SECURE_CRU_CLKGATE_CON(i), 0xffff0000); in clk_gate_con_disable()
340 for (i = 0; i < SECURE_SCRU_CLKGATE_CON_CNT; i++) in clk_gate_con_disable()
[all …]
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| /rk3399_ARM-atf/plat/arm/common/ |
| H A D | arm_dyn_cfg.c | 131 unsigned int i; in arm_bl2_dyn_cfg_init() local
146 for (i = 0; i < ARRAY_SIZE(config_ids); i++) { in arm_bl2_dyn_cfg_init()
148 cfg_mem_params = get_bl_mem_params_node(config_ids[i]); in arm_bl2_dyn_cfg_init()
151 "Couldn't find ", config_ids[i]); in arm_bl2_dyn_cfg_init()
155 dtb_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, config_ids[i]); in arm_bl2_dyn_cfg_init()
158 "Couldn't find ", config_ids[i]); in arm_bl2_dyn_cfg_init()
170 if (config_ids[i] != HW_CONFIG_ID) { in arm_bl2_dyn_cfg_init()
175 config_ids[i], in arm_bl2_dyn_cfg_init()
177 error_config_id = config_ids[i]; in arm_bl2_dyn_cfg_init()
186 config_ids[i], in arm_bl2_dyn_cfg_init()
[all …]
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| /rk3399_ARM-atf/drivers/renesas/rzg/qos/G2M/ |
| H A D | qos_init_g2m_v10.c | 109 uint32_t i; in qos_init_g2m_v10() local
111 for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) { in qos_init_g2m_v10()
112 mmio_write_64(QOSBW_FIX_QOS_BANK0 + i * 8U, mstat_fix[i]); in qos_init_g2m_v10()
113 mmio_write_64(QOSBW_FIX_QOS_BANK1 + i * 8U, mstat_fix[i]); in qos_init_g2m_v10()
115 for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) { in qos_init_g2m_v10()
116 mmio_write_64(QOSBW_BE_QOS_BANK0 + i * 8U, mstat_be[i]); in qos_init_g2m_v10()
117 mmio_write_64(QOSBW_BE_QOS_BANK1 + i * 8U, mstat_be[i]); in qos_init_g2m_v10()
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| /rk3399_ARM-atf/drivers/renesas/rcar/qos/D3/ |
| H A D | qos_init_d3.c | 110 uint32_t i; in qos_init_d3() local
112 for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) { in qos_init_d3()
113 io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]); in qos_init_d3()
114 io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]); in qos_init_d3()
116 for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) { in qos_init_d3()
117 io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]); in qos_init_d3()
118 io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]); in qos_init_d3()
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| /rk3399_ARM-atf/drivers/renesas/rcar/qos/M3/ |
| H A D | qos_init_m3_v10.c | 110 uint32_t i; in qos_init_m3_v10() local
112 for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) { in qos_init_m3_v10()
113 io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]); in qos_init_m3_v10()
114 io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]); in qos_init_m3_v10()
116 for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) { in qos_init_m3_v10()
117 io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]); in qos_init_m3_v10()
118 io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]); in qos_init_m3_v10()
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| /rk3399_ARM-atf/plat/intel/soc/common/lib/sha/ |
| H A D | sha.c | 65 int i; in sha384_finish() local
68 for (i = 0; i < SHA384_SUM_LEN / sizeof(uint64_t); i++) in sha384_finish()
69 PUT_UINT64_BE(ctx->state[i], digest, i * 8); in sha384_finish()
119 int i; in sha512_finish() local
122 for (i = 0; i < SHA512_SUM_LEN / sizeof(uint64_t); i++) in sha512_finish()
123 PUT_UINT64_BE(ctx->state[i], digest, i * 8); in sha512_finish()
140 int i; in sha512_transform() local
148 for (i = 0 ; i < 80; i += 8) { in sha512_transform()
149 if (!(i & 8)) { in sha512_transform()
152 if (i < 16) { in sha512_transform()
[all …]
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| /rk3399_ARM-atf/plat/rockchip/common/drivers/parameter/ |
| H A D | ddr_parameter.c | 54 uint32_t i, addr_offset, size_offset; in ddr_region_usage_parse() local
75 for (i = 0; i < p.ns_nr; i++) { in ddr_region_usage_parse()
82 p.ns_base[i] = RG_SIZE_MB(base); in ddr_region_usage_parse()
83 p.ns_top[i] = RG_SIZE_MB(top); in ddr_region_usage_parse()
115 for (i = 0; i < p.ns_nr; i++) { in ddr_region_usage_parse()
120 if (p.ns_top[i] == p.boundary) in ddr_region_usage_parse()
124 p.s_base[p.s_nr] = p.ns_top[i]; in ddr_region_usage_parse()
127 if (i + 1 < p.ns_nr) in ddr_region_usage_parse()
128 p.s_top[p.s_nr] = p.ns_base[i + 1]; in ddr_region_usage_parse()
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| /rk3399_ARM-atf/plat/mediatek/mt8195/drivers/spm/ |
| H A D | mt_spm_cond.c | 124 unsigned int blocked = 0U, i; in mt_spm_cond_check() local
131 for (i = 0U; i < PLAT_SPM_COND_MAX; i++) { in mt_spm_cond_check()
133 res->table_cg[i] = in mt_spm_cond_check()
134 (src->table_cg[i] & dest->table_cg[i]); in mt_spm_cond_check()
136 if (is_system_suspend && (res->table_cg[i] != 0U)) { in mt_spm_cond_check()
138 dest->name, i, idle_cg_info[i].addr, in mt_spm_cond_check()
139 res->table_cg[i]); in mt_spm_cond_check()
142 if (res->table_cg[i] != 0U) { in mt_spm_cond_check()
143 blocked |= (1U << i); in mt_spm_cond_check()
145 } else if ((src->table_cg[i] & dest->table_cg[i]) != 0U) { in mt_spm_cond_check()
[all …]
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| /rk3399_ARM-atf/drivers/nxp/auth/csf_hdr_parser/ |
| H A D | csf_hdr_parser.c | 54 int i, j = 0; in deploy_rotpk_hash_table() local
87 for (i = 0; i < SHA256_BYTES/4; i++) { in deploy_rotpk_hash_table()
88 srk_hash[i] = in deploy_rotpk_hash_table()
89 mmio_read_32((uintptr_t)&sfp_ccsr_regs->srk_hash[i]); in deploy_rotpk_hash_table()
93 for (i = 0; i < 8; i++) { in deploy_rotpk_hash_table()
94 VERBOSE("%x\n", *((uint32_t *)hash + i)); in deploy_rotpk_hash_table()
108 for (i = 0; i < num_srk; i++) { in deploy_rotpk_hash_table()
115 ret = hash_update(algo, ctx, srktbl[i].pkey, srktbl[i].key_len); in deploy_rotpk_hash_table()
121 ret = hash_final(algo, ctx, rotpk_hash_table[i], digest_size); in deploy_rotpk_hash_table()
125 VERBOSE("Table key %d HASH\n", i); in deploy_rotpk_hash_table()
[all …]
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| /rk3399_ARM-atf/plat/rockchip/rk3399/drivers/dram/ |
| H A D | suspend.c | 191 uint32_t i, tmp; in data_training() local
219 for (i = 0; i < 4; i++) { in data_training()
220 if (!(rank_mask & (1 << i))) in data_training()
223 select_per_cs_training_index(ch, i); in data_training()
230 (0x1 << 16) | (i << 24)); in data_training()
263 for (i = 0; i < rank; i++) { in data_training()
264 select_per_cs_training_index(ch, i); in data_training()
270 (0x1 << 8) | (i << 16)); in data_training()
309 for (i = 0; i < rank; i++) { in data_training()
310 select_per_cs_training_index(ch, i); in data_training()
[all …]
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| /rk3399_ARM-atf/plat/mediatek/drivers/apusys/apusys_rv/2.0/ |
| H A D | apusys_rv.c | 37 int i; in apusys_rv_mbox_mpu_init() local
39 for (i = 0; i < APU_MBOX_NUM; i++) { in apusys_rv_mbox_mpu_init()
40 mmio_write_32(APU_MBOX_FUNC_CFG(i), in apusys_rv_mbox_mpu_init()
42 (mbox_mpu_setting_tab[i].no_mpu << MBOX_NO_MPU_SHIFT))); in apusys_rv_mbox_mpu_init()
43 mmio_write_32(APU_MBOX_DOMAIN_CFG(i), in apusys_rv_mbox_mpu_init()
45 (mbox_mpu_setting_tab[i].rx_ns << MBOX_RX_NS_SHIFT) | in apusys_rv_mbox_mpu_init()
46 (mbox_mpu_setting_tab[i].rx_domain << MBOX_RX_DOMAIN_SHIFT) | in apusys_rv_mbox_mpu_init()
47 (mbox_mpu_setting_tab[i].tx_ns << MBOX_TX_NS_SHIFT) | in apusys_rv_mbox_mpu_init()
48 (mbox_mpu_setting_tab[i].tx_domain << MBOX_TX_DOMAIN_SHIFT))); in apusys_rv_mbox_mpu_init()
303 uint32_t i; in apusys_kernel_apusys_logtop_reg_dump() local
[all …]
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| /rk3399_ARM-atf/plat/mediatek/drivers/apusys/mt8188/ |
| H A D | apusys_security_ctrl_plat.c | 26 int i; in apusys_domain_remap_init() local
28 for (i = 0; i < ARRAY_SIZE(remap_domains); i++) { in apusys_domain_remap_init()
29 if (i < REG_DOMAIN_NUM) { in apusys_domain_remap_init()
30 lower_domain |= (remap_domains[i] << (i * REG_DOMAIN_BITS)); in apusys_domain_remap_init()
32 higher_domain |= (remap_domains[i] << in apusys_domain_remap_init()
33 ((i - REG_DOMAIN_NUM) * REG_DOMAIN_BITS)); in apusys_domain_remap_init()
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| /rk3399_ARM-atf/plat/mediatek/mt8173/drivers/crypt/ |
| H A D | crypt.c | 58 uint32_t i = (uint32_t)x1; in crypt_set_hdcp_key_ex() local
61 if (i > KEY_LEN) in crypt_set_hdcp_key_ex()
64 if (i < KEY_LEN) { in crypt_set_hdcp_key_ex()
77 crypt_write32(REG_D20 + 4 * i, GET_L32(x2)); in crypt_set_hdcp_key_ex()
78 crypt_write32(REG_D20 + 4 * i + 1, GET_H32(x2)); in crypt_set_hdcp_key_ex()
79 crypt_write32(REG_D20 + 4 * i + 2, GET_L32(x3)); in crypt_set_hdcp_key_ex()
80 crypt_write32(REG_D20 + 4 * i + 3, GET_H32(x3)); in crypt_set_hdcp_key_ex()
84 crypt_write32(REG_P71, 0x34 + 4 * i); in crypt_set_hdcp_key_ex()
85 crypt_write32(REG_P72, 0x34 + 4 * i); in crypt_set_hdcp_key_ex()
90 crypt_write32(REG_P69, 0x34 + 4 * i + j); in crypt_set_hdcp_key_ex()
[all …]
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| /rk3399_ARM-atf/plat/renesas/rcar_gen5/ |
| H A D | plat_pm.c | 95 for (unsigned int i = 0U; i < PLATFORM_CORE_COUNT; i++) in rcar_pwr_domain_suspend() local
96 gicv3_rdistif_save(i, &rdist_ctx[i]); in rcar_pwr_domain_suspend()
116 for (unsigned int i = 0U; i < PLATFORM_CORE_COUNT; i++) in rcar_pwr_domain_suspend_finish() local
117 gicv3_rdistif_init_restore(i, &rdist_ctx[i]); in rcar_pwr_domain_suspend_finish()
167 uint64_t i; in rcar_validate_power_state() local
176 for (i = MPIDR_AFFLVL0; i <= (uint64_t)pwr_lvl; i++) { in rcar_validate_power_state()
177 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; in rcar_validate_power_state()
190 uint64_t i; in rcar_get_sys_suspend_power_state() local
192 for (i = MPIDR_AFFLVL0; i <= (uint64_t)PLAT_MAX_PWR_LVL; i++) { in rcar_get_sys_suspend_power_state()
193 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; in rcar_get_sys_suspend_power_state()
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| /rk3399_ARM-atf/plat/rockchip/px30/drivers/soc/ |
| H A D | soc.h | 34 #define GRF_SOC_CON(i) (0x0400 + (i) * 4) argument
60 #define CRU_CLKSELS_CON(i) (CRU_CLKSEL_CON + (i) * 4) argument
64 #define CRU_CLKGATES_CON(i) (CRU_CLKGATE_CON + (i) * 4) argument
74 #define CRU_CONS_GATEID(i) (16 * (i)) argument
92 #define CRU_PLL_CONS(id, i) ((id) * 0x20 + (i) * 4) argument
93 #define PLL_CON(i) ((i) * 4) argument
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| /rk3399_ARM-atf/plat/mediatek/mt8183/drivers/devapc/ |
| H A D | devapc.c | 181 int i; in dump_devapc() local
185 for (i = 0; i < 13; i++) { in dump_devapc()
189 i, mmio_read_32(DEVAPC_INFRA_D0_APC_0 + i * 4), in dump_devapc()
190 i, mmio_read_32(DEVAPC_INFRA_D0_APC_0 + 0x100 + i * 4), in dump_devapc()
191 i, mmio_read_32(DEVAPC_INFRA_D0_APC_0 + 0x200 + i * 4)); in dump_devapc()
194 for (i = 0; i < 9; i++) { in dump_devapc()
198 i, mmio_read_32(DEVAPC_MM_D0_APC_0 + i * 4), in dump_devapc()
199 i, mmio_read_32(DEVAPC_MM_D0_APC_0 + 0x100 + i * 4), in dump_devapc()
200 i, mmio_read_32(DEVAPC_MM_D0_APC_0 + 0x200 + i * 4)); in dump_devapc()
203 for (i = 0; i < 4; i++) { in dump_devapc()
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