1 /*
2 * Copyright (c) 2020-2025, Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8
9 #include <libfdt.h>
10 #include <tc_plat.h>
11
12 #include <arch_helpers.h>
13 #include <common/bl_common.h>
14 #include <common/debug.h>
15 #include <drivers/arm/css/css_mhu_doorbell.h>
16 #include <drivers/arm/css/scmi.h>
17 #include <drivers/arm/dsu.h>
18 #include <drivers/arm/sbsa.h>
19 #include <lib/fconf/fconf.h>
20 #include <lib/fconf/fconf_dyn_cfg_getter.h>
21 #include <plat/arm/common/plat_arm.h>
22 #include <plat/common/platform.h>
23
24 #ifdef PLATFORM_TEST_TFM_TESTSUITE
25 #include <psa/crypto_platform.h>
26 #include <psa/crypto_types.h>
27 #include <psa/crypto_values.h>
28 #endif /* PLATFORM_TEST_TFM_TESTSUITE */
29 #include <psa/error.h>
30
31 #include <plat/common/platform.h>
32 #include <tc_rse_comms.h>
33
34 #ifdef PLATFORM_TEST_TFM_TESTSUITE
35 /*
36 * We pretend using an external RNG (through MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG
37 * mbedTLS config option) so we need to provide an implementation of
38 * mbedtls_psa_external_get_random(). Provide a fake one, since we do not
39 * actually use any of external RNG and this function is only needed during
40 * the execution of TF-M testsuite during exporting the public part of the
41 * delegated attestation key.
42 */
mbedtls_psa_external_get_random(mbedtls_psa_external_random_context_t * context,uint8_t * output,size_t output_size,size_t * output_length)43 psa_status_t mbedtls_psa_external_get_random(
44 mbedtls_psa_external_random_context_t *context,
45 uint8_t *output, size_t output_size,
46 size_t *output_length)
47 {
48 for (size_t i = 0U; i < output_size; i++) {
49 output[i] = (uint8_t)(read_cntpct_el0() & 0xFFU);
50 }
51
52 *output_length = output_size;
53
54 return PSA_SUCCESS;
55 }
56 #endif /* PLATFORM_TEST_TFM_TESTSUITE */
57
58 static scmi_channel_plat_info_t tc_scmi_plat_info = {
59 .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE,
60 .db_reg_addr = PLAT_CSS_MHU_BASE + MHU_V3_SENDER_REG_SET(0),
61 .db_preserve_mask = 0xfffffffe,
62 .db_modify_mask = 0x1,
63 .ring_doorbell = &mhu_ring_doorbell,
64 };
65
66 /* the bottom 3 AMU group 1 counters */
67 #define MPMM_GEARS ((1 << 0) | (1 << 1) | (1 << 2))
68
69 uint16_t plat_amu_aux_enables[PLATFORM_CORE_COUNT] = {
70 MPMM_GEARS, MPMM_GEARS, MPMM_GEARS, MPMM_GEARS,
71 MPMM_GEARS, MPMM_GEARS, MPMM_GEARS, MPMM_GEARS,
72 #if PLATFORM_CORE_COUNT == 14
73 MPMM_GEARS, MPMM_GEARS, MPMM_GEARS, MPMM_GEARS,
74 MPMM_GEARS, MPMM_GEARS
75 #endif
76 };
77
78 const dsu_driver_data_t plat_dsu_data = {
79 .clusterpwrdwn_pwrdn = false,
80 .clusterpwrdwn_memret = false,
81 .clusterpwrctlr_cachepwr = CLUSTERPWRCTLR_CACHEPWR_RESET,
82 .clusterpwrctlr_funcret = CLUSTERPWRCTLR_FUNCRET_RESET
83 };
84
enable_ns_mcn_pmu(void)85 static void enable_ns_mcn_pmu(void)
86 {
87 /*
88 * Enable non-secure access to MCN PMU registers
89 */
90 for (int i = 0; i < MCN_INSTANCES; i++) {
91 uintptr_t mcn_scr = MCN_MICROARCH_BASE_ADDR(i) +
92 MCN_SCR_OFFSET;
93 mmio_setbits_32(mcn_scr, 1 << MCN_SCR_PMU_BIT);
94 }
95 }
96
97 #if TARGET_PLATFORM == 3
set_mcn_slc_alloc_mode(void)98 static void set_mcn_slc_alloc_mode(void)
99 {
100 /*
101 * SLC WRALLOCMODE and RDALLOCMODE are configured by default to
102 * 0b01 (always alloc), configure both to 0b10 (use bus signal
103 * attribute from interface).
104 */
105 for (int i = 0; i < MCN_INSTANCES; i++) {
106 uintptr_t slccfg_ctl_ns = MCN_MPAM_NS_BASE_ADDR(i) +
107 MPAM_SLCCFG_CTL_OFFSET;
108 uintptr_t slccfg_ctl_s = MCN_MPAM_S_BASE_ADDR(i) +
109 MPAM_SLCCFG_CTL_OFFSET;
110
111 mmio_clrsetbits_32(slccfg_ctl_ns,
112 (SLC_RDALLOCMODE_MASK | SLC_WRALLOCMODE_MASK),
113 (SLC_ALLOC_BUS_SIGNAL_ATTR << SLC_RDALLOCMODE_SHIFT) |
114 (SLC_ALLOC_BUS_SIGNAL_ATTR << SLC_WRALLOCMODE_SHIFT));
115 mmio_clrsetbits_32(slccfg_ctl_s,
116 (SLC_RDALLOCMODE_MASK | SLC_WRALLOCMODE_MASK),
117 (SLC_ALLOC_BUS_SIGNAL_ATTR << SLC_RDALLOCMODE_SHIFT) |
118 (SLC_ALLOC_BUS_SIGNAL_ATTR << SLC_WRALLOCMODE_SHIFT));
119 }
120 }
121 #endif
122
bl31_platform_setup(void)123 void bl31_platform_setup(void)
124 {
125 psa_status_t status;
126
127 tc_bl31_common_platform_setup();
128 enable_ns_mcn_pmu();
129 #if TARGET_PLATFORM == 3
130 set_mcn_slc_alloc_mode();
131 plat_arm_ni_setup(NCI_BASE_ADDR);
132 #endif
133
134 /* Initialise RSE communication channel */
135 status = plat_rse_comms_init();
136 if (status != PSA_SUCCESS) {
137 ERROR("Failed to initialize RSE communication channel - psa_status = %d\n", status);
138 }
139 }
140
plat_css_get_scmi_info(unsigned int channel_id __unused)141 scmi_channel_plat_info_t *plat_css_get_scmi_info(unsigned int channel_id __unused)
142 {
143
144 return &tc_scmi_plat_info;
145
146 }
147
bl31_early_platform_setup2(u_register_t arg0,u_register_t arg1,u_register_t arg2,u_register_t arg3)148 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
149 u_register_t arg2, u_register_t arg3)
150 {
151 /* Initialize the console to provide early debug support */
152 arm_console_boot_init();
153
154 arm_bl31_early_platform_setup(arg0, arg1, arg2, arg3);
155
156 #if !TRANSFER_LIST
157 /* Fill the properties struct with the info from the config dtb */
158 fconf_populate("FW_CONFIG", arg1);
159 #endif
160 }
161
162 #ifdef PLATFORM_TESTS
tc_run_platform_tests(void)163 static __dead2 void tc_run_platform_tests(void)
164 {
165 int tests_failed;
166
167 printf("\nStarting platform tests...\n");
168
169 #ifdef PLATFORM_TEST_NV_COUNTERS
170 tests_failed = nv_counter_test();
171 #elif PLATFORM_TEST_ROTPK
172 tests_failed = rotpk_test();
173 #elif PLATFORM_TEST_TFM_TESTSUITE
174 tests_failed = run_platform_tests();
175 #endif
176
177 printf("Platform tests %s.\n",
178 (tests_failed != 0) ? "failed" : "succeeded");
179
180 /* Suspend booting, no matter the tests outcome. */
181 printf("Suspend booting...\n");
182 plat_error_handler(-1);
183 }
184 #endif
185
tc_bl31_common_platform_setup(void)186 void tc_bl31_common_platform_setup(void)
187 {
188 arm_bl31_platform_setup();
189
190 gic_set_gicr_frames(arm_gicr_base_addrs);
191
192 #ifdef PLATFORM_TESTS
193 tc_run_platform_tests();
194 #endif
195 }
196
plat_arm_psci_override_pm_ops(plat_psci_ops_t * ops)197 const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops)
198 {
199 return css_scmi_override_pm_ops(ops);
200 }
201
bl31_plat_arch_setup(void)202 void __init bl31_plat_arch_setup(void)
203 {
204 arm_bl31_plat_arch_setup();
205
206 /*
207 * When TRANSFER_LIST is enabled, HW_CONFIG is included in Transfer List
208 * as an entry with the tag TL_TAG_FDT. In this case, the configuration
209 * is already available, so the fconf_populate mechanism is not needed.
210 * The code block below is only required when TRANSFER_LIST is not used.
211 */
212 #if !TRANSFER_LIST
213 /* HW_CONFIG was also loaded by BL2 */
214 const struct dyn_cfg_dtb_info_t *hw_config_info;
215
216 hw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, HW_CONFIG_ID);
217 assert(hw_config_info != NULL);
218
219 fconf_populate("HW_CONFIG", hw_config_info->config_addr);
220 #endif
221 }
222
223 #if defined(SPD_spmd) && (SPMC_AT_EL3 == 0)
tc_bl31_plat_runtime_setup(void)224 void tc_bl31_plat_runtime_setup(void)
225 {
226 /* Start secure watchdog timer. */
227 plat_arm_secure_wdt_start();
228
229 arm_bl31_plat_runtime_setup();
230 }
231
bl31_plat_runtime_setup(void)232 void bl31_plat_runtime_setup(void)
233 {
234 tc_bl31_plat_runtime_setup();
235 }
236
237 /*
238 * Platform handler for Group0 secure interrupt.
239 */
plat_spmd_handle_group0_interrupt(uint32_t intid)240 int plat_spmd_handle_group0_interrupt(uint32_t intid)
241 {
242 /* Trusted Watchdog timer is the only source of Group0 interrupt now. */
243 if (intid == SBSA_SECURE_WDOG_INTID) {
244 /* Refresh the timer. */
245 plat_arm_secure_wdt_refresh();
246
247 return 0;
248 }
249
250 return -1;
251 }
252 #endif /*defined(SPD_spmd) && (SPMC_AT_EL3 == 0)*/
253