1*010d6ae3SXiaoDong Huang /* 2*010d6ae3SXiaoDong Huang * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. 3*010d6ae3SXiaoDong Huang * 4*010d6ae3SXiaoDong Huang * SPDX-License-Identifier: BSD-3-Clause 5*010d6ae3SXiaoDong Huang */ 6*010d6ae3SXiaoDong Huang 7*010d6ae3SXiaoDong Huang #ifndef __SOC_H__ 8*010d6ae3SXiaoDong Huang #define __SOC_H__ 9*010d6ae3SXiaoDong Huang 10*010d6ae3SXiaoDong Huang #include <plat_private.h> 11*010d6ae3SXiaoDong Huang 12*010d6ae3SXiaoDong Huang #ifndef BITS_WMSK 13*010d6ae3SXiaoDong Huang #define BITS_WMSK(msk, shift) ((msk) << (shift + REG_MSK_SHIFT)) 14*010d6ae3SXiaoDong Huang #endif 15*010d6ae3SXiaoDong Huang 16*010d6ae3SXiaoDong Huang enum plls_id { 17*010d6ae3SXiaoDong Huang APLL_ID = 0, 18*010d6ae3SXiaoDong Huang DPLL_ID, 19*010d6ae3SXiaoDong Huang CPLL_ID, 20*010d6ae3SXiaoDong Huang NPLL_ID, 21*010d6ae3SXiaoDong Huang GPLL_ID, 22*010d6ae3SXiaoDong Huang END_PLL_ID, 23*010d6ae3SXiaoDong Huang }; 24*010d6ae3SXiaoDong Huang 25*010d6ae3SXiaoDong Huang enum pll_mode { 26*010d6ae3SXiaoDong Huang SLOW_MODE, 27*010d6ae3SXiaoDong Huang NORM_MODE, 28*010d6ae3SXiaoDong Huang DEEP_SLOW_MODE, 29*010d6ae3SXiaoDong Huang }; 30*010d6ae3SXiaoDong Huang 31*010d6ae3SXiaoDong Huang /*************************************************************************** 32*010d6ae3SXiaoDong Huang * GRF 33*010d6ae3SXiaoDong Huang ***************************************************************************/ 34*010d6ae3SXiaoDong Huang #define GRF_SOC_CON(i) (0x0400 + (i) * 4) 35*010d6ae3SXiaoDong Huang #define GRF_PD_VO_CON0 0x0434 36*010d6ae3SXiaoDong Huang #define GRF_SOC_STATUS0 0x0480 37*010d6ae3SXiaoDong Huang #define GRF_CPU_STATUS0 0x0520 38*010d6ae3SXiaoDong Huang #define GRF_CPU_STATUS1 0x0524 39*010d6ae3SXiaoDong Huang #define GRF_SOC_NOC_CON0 0x0530 40*010d6ae3SXiaoDong Huang #define GRF_SOC_NOC_CON1 0x0534 41*010d6ae3SXiaoDong Huang 42*010d6ae3SXiaoDong Huang #define CKECK_WFE_MSK 0x1 43*010d6ae3SXiaoDong Huang #define CKECK_WFI_MSK 0x10 44*010d6ae3SXiaoDong Huang #define CKECK_WFEI_MSK 0x11 45*010d6ae3SXiaoDong Huang 46*010d6ae3SXiaoDong Huang #define GRF_SOC_CON2_NSWDT_RST_EN 12 47*010d6ae3SXiaoDong Huang 48*010d6ae3SXiaoDong Huang /*************************************************************************** 49*010d6ae3SXiaoDong Huang * cru 50*010d6ae3SXiaoDong Huang ***************************************************************************/ 51*010d6ae3SXiaoDong Huang #define CRU_MODE 0xa0 52*010d6ae3SXiaoDong Huang #define CRU_MISC 0xa4 53*010d6ae3SXiaoDong Huang #define CRU_GLB_CNT_TH 0xb0 54*010d6ae3SXiaoDong Huang #define CRU_GLB_RST_ST 0xb4 55*010d6ae3SXiaoDong Huang #define CRU_GLB_SRST_FST 0xb8 56*010d6ae3SXiaoDong Huang #define CRU_GLB_SRST_SND 0xbc 57*010d6ae3SXiaoDong Huang #define CRU_GLB_RST_CON 0xc0 58*010d6ae3SXiaoDong Huang 59*010d6ae3SXiaoDong Huang #define CRU_CLKSEL_CON 0x100 60*010d6ae3SXiaoDong Huang #define CRU_CLKSELS_CON(i) (CRU_CLKSEL_CON + (i) * 4) 61*010d6ae3SXiaoDong Huang #define CRU_CLKSEL_CON_CNT 60 62*010d6ae3SXiaoDong Huang 63*010d6ae3SXiaoDong Huang #define CRU_CLKGATE_CON 0x200 64*010d6ae3SXiaoDong Huang #define CRU_CLKGATES_CON(i) (CRU_CLKGATE_CON + (i) * 4) 65*010d6ae3SXiaoDong Huang #define CRU_CLKGATES_CON_CNT 18 66*010d6ae3SXiaoDong Huang 67*010d6ae3SXiaoDong Huang #define CRU_SOFTRST_CON 0x300 68*010d6ae3SXiaoDong Huang #define CRU_SOFTRSTS_CON(n) (CRU_SOFTRST_CON + ((n) * 4)) 69*010d6ae3SXiaoDong Huang #define CRU_SOFTRSTS_CON_CNT 12 70*010d6ae3SXiaoDong Huang 71*010d6ae3SXiaoDong Huang #define CRU_AUTOCS_CON0(id) (0x400 + (id) * 8) 72*010d6ae3SXiaoDong Huang #define CRU_AUTOCS_CON1(id) (0x404 + (id) * 8) 73*010d6ae3SXiaoDong Huang 74*010d6ae3SXiaoDong Huang #define CRU_CONS_GATEID(i) (16 * (i)) 75*010d6ae3SXiaoDong Huang #define GATE_ID(reg, bit) ((reg) * 16 + (bit)) 76*010d6ae3SXiaoDong Huang 77*010d6ae3SXiaoDong Huang #define CRU_GLB_SRST_FST_VALUE 0xfdb9 78*010d6ae3SXiaoDong Huang #define CRU_GLB_SRST_SND_VALUE 0xeca8 79*010d6ae3SXiaoDong Huang 80*010d6ae3SXiaoDong Huang #define CRU_GLB_RST_TSADC_EXT 6 81*010d6ae3SXiaoDong Huang #define CRU_GLB_RST_WDT_EXT 7 82*010d6ae3SXiaoDong Huang 83*010d6ae3SXiaoDong Huang #define CRU_GLB_CNT_RST_MSK 0xffff 84*010d6ae3SXiaoDong Huang #define CRU_GLB_CNT_RST_1MS 0x5DC0 85*010d6ae3SXiaoDong Huang 86*010d6ae3SXiaoDong Huang #define CRU_GLB_RST_TSADC_FST BIT(0) 87*010d6ae3SXiaoDong Huang #define CRU_GLB_RST_WDT_FST BIT(1) 88*010d6ae3SXiaoDong Huang 89*010d6ae3SXiaoDong Huang /*************************************************************************** 90*010d6ae3SXiaoDong Huang * pll 91*010d6ae3SXiaoDong Huang ***************************************************************************/ 92*010d6ae3SXiaoDong Huang #define CRU_PLL_CONS(id, i) ((id) * 0x20 + (i) * 4) 93*010d6ae3SXiaoDong Huang #define PLL_CON(i) ((i) * 4) 94*010d6ae3SXiaoDong Huang #define PLL_CON_CNT 5 95*010d6ae3SXiaoDong Huang #define PLL_LOCK_MSK BIT(10) 96*010d6ae3SXiaoDong Huang #define PLL_MODE_SHIFT(id) ((id) == CPLL_ID ? \ 97*010d6ae3SXiaoDong Huang 2 : \ 98*010d6ae3SXiaoDong Huang ((id) == DPLL_ID ? 4 : 2 * (id))) 99*010d6ae3SXiaoDong Huang #define PLL_MODE_MSK(id) (0x3 << PLL_MODE_SHIFT(id)) 100*010d6ae3SXiaoDong Huang 101*010d6ae3SXiaoDong Huang #define PLL_LOCKED_TIMEOUT 600000U 102*010d6ae3SXiaoDong Huang 103*010d6ae3SXiaoDong Huang /*************************************************************************** 104*010d6ae3SXiaoDong Huang * GPIO 105*010d6ae3SXiaoDong Huang ***************************************************************************/ 106*010d6ae3SXiaoDong Huang #define SWPORTA_DR 0x00 107*010d6ae3SXiaoDong Huang #define SWPORTA_DDR 0x04 108*010d6ae3SXiaoDong Huang #define GPIO_INTEN 0x30 109*010d6ae3SXiaoDong Huang #define GPIO_INT_STATUS 0x40 110*010d6ae3SXiaoDong Huang #define GPIO_NUMS 4 111*010d6ae3SXiaoDong Huang 112*010d6ae3SXiaoDong Huang void clk_gate_con_save(uint32_t *clkgt_save); 113*010d6ae3SXiaoDong Huang void clk_gate_con_restore(uint32_t *clkgt_save); 114*010d6ae3SXiaoDong Huang void clk_gate_con_disable(void); 115*010d6ae3SXiaoDong Huang 116*010d6ae3SXiaoDong Huang void px30_soc_reset_config(void); 117*010d6ae3SXiaoDong Huang 118*010d6ae3SXiaoDong Huang #endif /* __SOC_H__ */ 119