191 	uint32_t i, tmp;  in data_training()  local
219 		for (i = 0; i < 4; i++) {  in data_training()
220 			if (!(rank_mask & (1 << i)))  in data_training()
223 			select_per_cs_training_index(ch, i);  in data_training()
230 					   (0x1 << 16) | (i << 24));  in data_training()
263 		for (i = 0; i < rank; i++) {  in data_training()
264 			select_per_cs_training_index(ch, i);  in data_training()
270 					   (0x1 << 8) | (i << 16));  in data_training()
309 		for (i = 0; i < rank; i++) {  in data_training()
310 			select_per_cs_training_index(ch, i);  in data_training()
320 					   (0x1 << 16) | (i << 24));  in data_training()
357 		for (i = 0; i < rank; i++) {  in data_training()
358 			select_per_cs_training_index(ch, i);  in data_training()
365 					   (0x1 << 8) | (i << 24));  in data_training()
390 		for (i = 0; i < 4; i++) {  in data_training()
391 			if (!(rank_mask & (1 << i)))  in data_training()
394 			select_per_cs_training_index(ch, i);  in data_training()
406 					   (0x1 << 8) | (i << 16));  in data_training()
455 	unsigned int i;  in dram_all_config()  local
457 	for (i = 0; i < 2; i++) {  in dram_all_config()
458 		struct rk3399_sdram_channel *info = &sdram_params->ch[i];  in dram_all_config()
461 		if (sdram_params->ch[i].col == 0)  in dram_all_config()
464 		mmio_write_32(MSCH_BASE(i) + MSCH_DDRTIMINGA0,  in dram_all_config()
466 		mmio_write_32(MSCH_BASE(i) + MSCH_DDRTIMINGB0,  in dram_all_config()
468 		mmio_write_32(MSCH_BASE(i) + MSCH_DDRTIMINGC0,  in dram_all_config()
470 		mmio_write_32(MSCH_BASE(i) + MSCH_DEVTODEV0,  in dram_all_config()
472 		mmio_write_32(MSCH_BASE(i) + MSCH_DDRMODE, noc->ddrmode.d32);  in dram_all_config()
475 		if (sdram_params->ch[i].rank == 1)  in dram_all_config()
476 			mmio_setbits_32(CTL_REG(i, 276), 1 << 17);  in dram_all_config()
495 	uint32_t tmp, tmp1, tmp2, i;  in pctl_cfg()  local
537 	for (i = 0; i < 4; i++)  in pctl_cfg()
538 		sram_regcpy(PHY_REG(ch, 128 * i),  in pctl_cfg()
541 	for (i = 0; i < 3; i++)  in pctl_cfg()
542 		sram_regcpy(PHY_REG(ch, 512 + 128 * i),  in pctl_cfg()
543 				(uintptr_t)&phy_regs->phy512[i][0], 38);  in pctl_cfg()
701 	uint32_t ch, byte, i;  in dmc_suspend()  local
709 	for (i = 0; i < PLL_CON_COUNT; i++)  in dmc_suspend()
710 		dpll_data[i] = mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, i));  in dmc_suspend()
739 	for (i = 0; i < 3; i++)  in dmc_suspend()
740 		dram_regcpy((uintptr_t)&phy_regs->phy512[i][0],  in dmc_suspend()
741 			    PHY_REG(0, 512 + 128 * i), 38);  in dmc_suspend()