1 /*
2 * Copyright (c) 2025, Renesas Electronics Corporation. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <errno.h>
8
9 #include <arch_helpers.h>
10 #include <common/bl_common.h>
11 #include <common/debug.h>
12 #include <drivers/arm/cci.h>
13 #include <drivers/arm/gicv3.h>
14 #include <lib/bakery_lock.h>
15 #include <lib/mmio.h>
16 #include <lib/psci/psci.h>
17 #include <plat/common/platform.h>
18 #include "pwrc.h"
19 #include "timer.h"
20
21 #include "platform_def.h"
22 #include "rcar_def.h"
23 #include "rcar_private.h"
24
25 #define SYSTEM_PWR_STATE(s) ((s)->pwr_domain_state[PLAT_MAX_PWR_LVL])
26 #define CORE_PWR_STATE(s) ((s)->pwr_domain_state[MPIDR_AFFLVL0])
27
28 static uintptr_t rcar_sec_entrypoint;
29 static gicv3_redist_ctx_t rdist_ctx[PLATFORM_CORE_COUNT];
30 static gicv3_dist_ctx_t dist_ctx;
31
rcar_program_mailbox(u_register_t mpidr,uintptr_t address)32 static void rcar_program_mailbox(u_register_t mpidr, uintptr_t address)
33 {
34 uintptr_t range;
35 mailbox_t *rcar_mboxes = (mailbox_t *) MBOX_BASE;
36 int linear_id = plat_core_pos_by_mpidr(mpidr);
37
38 if (linear_id < 0) {
39 ERROR("BL3-1 : The value of passed MPIDR is invalid.");
40 panic();
41 }
42 rcar_mboxes[linear_id].value = address;
43 range = (uintptr_t)(&rcar_mboxes[linear_id]);
44
45 flush_dcache_range(range, sizeof(mailbox_t));
46 }
47
rcar_cpu_standby(plat_local_state_t cpu_state)48 static void rcar_cpu_standby(plat_local_state_t cpu_state)
49 {
50 u_register_t scr_el3 = read_scr_el3();
51
52 write_scr_el3(scr_el3 | SCR_IRQ_BIT);
53 dsb();
54 wfi();
55 write_scr_el3(scr_el3);
56 }
57
rcar_pwr_domain_on(u_register_t mpidr)58 static int rcar_pwr_domain_on(u_register_t mpidr)
59 {
60 rcar_program_mailbox(mpidr, rcar_sec_entrypoint);
61 rcar_scmi_cpuon(mpidr);
62
63 return PSCI_E_SUCCESS;
64 }
65
rcar_pwr_domain_on_finish(const psci_power_state_t * target_state)66 static void rcar_pwr_domain_on_finish(const psci_power_state_t *target_state)
67 {
68 u_register_t mpidr = read_mpidr_el1();
69
70 rcar_pwrc_disable_interrupt_wakeup(mpidr);
71 rcar_program_mailbox(mpidr, 0U);
72 }
73
rcar_pwr_domain_off(const psci_power_state_t * target_state)74 static void rcar_pwr_domain_off(const psci_power_state_t *target_state)
75 {
76 u_register_t mpidr = read_mpidr_el1();
77
78 rcar_pwrc_disable_interrupt_wakeup(mpidr);
79
80 rcar_scmi_cpuoff(target_state);
81 }
82
rcar_pwr_domain_suspend(const psci_power_state_t * target_state)83 static void rcar_pwr_domain_suspend(const psci_power_state_t *target_state)
84 {
85 u_register_t mpidr = read_mpidr_el1();
86
87 if (CORE_PWR_STATE(target_state) != PLAT_MAX_OFF_STATE) {
88 return;
89 }
90
91 rcar_program_mailbox(mpidr, rcar_sec_entrypoint);
92 rcar_pwrc_enable_interrupt_wakeup(mpidr);
93
94 if (SYSTEM_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) {
95 for (unsigned int i = 0U; i < PLATFORM_CORE_COUNT; i++)
96 gicv3_rdistif_save(i, &rdist_ctx[i]);
97 gicv3_distif_save(&dist_ctx);
98 }
99 }
100
rcar_pwr_domain_suspend_finish(const psci_power_state_t * target_state)101 static void rcar_pwr_domain_suspend_finish(const psci_power_state_t
102 *target_state)
103 {
104 u_register_t mpidr = read_mpidr_el1();
105
106 if (SYSTEM_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) {
107 rcar_pwrc_restore_timer_state();
108
109 plat_rcar_scmi_setup();
110 }
111
112 rcar_pwrc_disable_interrupt_wakeup(mpidr);
113 rcar_program_mailbox(mpidr, 0U);
114 if (SYSTEM_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) {
115 gicv3_distif_init_restore(&dist_ctx);
116 for (unsigned int i = 0U; i < PLATFORM_CORE_COUNT; i++)
117 gicv3_rdistif_init_restore(i, &rdist_ctx[i]);
118 }
119 }
120
rcar_system_off(void)121 static void __dead2 rcar_system_off(void)
122 {
123 u_register_t mpidr = read_mpidr_el1();
124 uint32_t rtn_on;
125
126 rtn_on = rcar_pwrc_cpu_on_check(mpidr);
127
128 if (rtn_on > 0U) {
129 panic();
130 }
131
132 rcar_scmi_sys_shutdown();
133
134 wfi();
135 ERROR("RCAR System Off: operation not handled.\n");
136 panic();
137 }
138
rcar_system_reset(void)139 static void __dead2 rcar_system_reset(void)
140 {
141 rcar_scmi_sys_reboot();
142
143 wfi();
144
145 ERROR("RCAR System Reset: operation not handled.\n");
146 panic();
147 }
148
rcar_pwr_domain_pwr_down_wfi(const psci_power_state_t * target_state)149 static void __dead2 rcar_pwr_domain_pwr_down_wfi(const psci_power_state_t *target_state)
150 {
151
152 if (SYSTEM_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) {
153 rcar_pwrc_suspend_to_ram();
154 }
155
156 wfi();
157
158 ERROR("RCAR Power Down: operation not handled.\n");
159 panic();
160 }
161
rcar_validate_power_state(unsigned int power_state,psci_power_state_t * req_state)162 static int rcar_validate_power_state(unsigned int power_state,
163 psci_power_state_t *req_state)
164 {
165 uint32_t pwr_lvl = psci_get_pstate_pwrlvl(power_state);
166 uint32_t pstate = psci_get_pstate_type(power_state);
167 uint64_t i;
168
169 if (pstate == PSTATE_TYPE_STANDBY) {
170 if (pwr_lvl != MPIDR_AFFLVL0) {
171 return PSCI_E_INVALID_PARAMS;
172 }
173
174 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE;
175 } else {
176 for (i = MPIDR_AFFLVL0; i <= (uint64_t)pwr_lvl; i++) {
177 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE;
178 }
179 }
180
181 if (psci_get_pstate_id(power_state) != 0U) {
182 return PSCI_E_INVALID_PARAMS;
183 }
184
185 return PSCI_E_SUCCESS;
186 }
187
rcar_get_sys_suspend_power_state(psci_power_state_t * req_state)188 static void rcar_get_sys_suspend_power_state(psci_power_state_t *req_state)
189 {
190 uint64_t i;
191
192 for (i = MPIDR_AFFLVL0; i <= (uint64_t)PLAT_MAX_PWR_LVL; i++) {
193 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE;
194 }
195 }
196
197 static plat_psci_ops_t rcar_plat_psci_ops = {
198 .cpu_standby = rcar_cpu_standby,
199 .pwr_domain_on = rcar_pwr_domain_on,
200 .pwr_domain_off = rcar_pwr_domain_off,
201 .pwr_domain_suspend = rcar_pwr_domain_suspend,
202 .pwr_domain_on_finish = rcar_pwr_domain_on_finish,
203 .pwr_domain_suspend_finish = rcar_pwr_domain_suspend_finish,
204 .system_off = rcar_system_off,
205 .system_reset = rcar_system_reset,
206 .validate_power_state = rcar_validate_power_state,
207 .pwr_domain_pwr_down = rcar_pwr_domain_pwr_down_wfi,
208 .get_sys_suspend_power_state = rcar_get_sys_suspend_power_state,
209 };
210
plat_setup_psci_ops(uintptr_t sec_entrypoint,const plat_psci_ops_t ** psci_ops)211 int plat_setup_psci_ops(uintptr_t sec_entrypoint, const plat_psci_ops_t **psci_ops)
212 {
213 *psci_ops = plat_rcar_psci_override_pm_ops(&rcar_plat_psci_ops);
214 rcar_sec_entrypoint = sec_entrypoint;
215
216 return 0;
217 }
218