| /OK3568_Linux_fs/kernel/Documentation/fb/ |
| H A D | viafb.modes | 10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
25 # Polarity negative negative
28 mode "640x480-60"
31 timings 39722 48 16 33 10 96 2 endmode mode "480x640-60"
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
50 # Polarity negative negative
52 mode "640x480-75"
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
71 # Polarity negative negative
73 mode "640x480-85"
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| H A D | pxafb.rst | 10 modprobe pxafb options=vmem:2M,mode:640x480-8,passive
14 video=pxafb:vmem:2M,mode:640x480-8,passive
21 mode:XRESxYRES[-BPP]
45 vsynclen:VSYNC == LCCR2_VSW + 1
65 hsync:HSYNC, vsync:VSYNC
68 high.
74 outputen:POLARITY
76 Output Enable Polarity. 0 => active low, 1 => active high
78 pixclockpol:POLARITY
80 pixel clock polarity
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/regulator/ |
| H A D | richtek,rtmv20-regulator.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/regulator/richtek,rtmv20-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - ChiYuan Huang <cy_huang@richtek.com>
16 There're still four pins for camera control, two inputs (strobe and vsync),
18 supply, vsync input from IR camera, and fsin1/fsin2 output for the optional.
27 wakeup-source: true
32 enable-gpios:
36 richtek,ld-pulse-delay-us:
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| /OK3568_Linux_fs/kernel/include/media/i2c/ |
| H A D | tvp7002.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* Texas Instruments Triple 8-/10-BIT 165-/110-MSPS Video and Graphics
6 * Author: Santiago Nunez-Corrales <santiago.nunez@ridgerun.com>
19 * struct tvp7002_config - Platform dependent data
20 *@clk_polarity: Clock polarity
21 * 0 - Data clocked out on rising edge of DATACLK signal
22 * 1 - Data clocked out on falling edge of DATACLK signal
23 *@hs_polarity: HSYNC polarity
24 * 0 - Active low HSYNC output, 1 - Active high HSYNC output
25 *@vs_polarity: VSYNC Polarity
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| /OK3568_Linux_fs/kernel/arch/sh/include/asm/ |
| H A D | sh7760fb.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * sh7760fb.h -- platform data for SH7760/SH7763 LCDC framebuffer driver.
5 * (c) 2006-2008 MSC Vertriebsges.m.b.H.,
19 /* The LCDC dma engine always sets bits 27-26 to 1: this is Area3 */
75 /* HSYNC polarity inversion */
78 /* VSYNC polarity inversion */
81 /* DISPLAY-ENABLE polarity inversion */
84 /* DISPLAY DATA BUS polarity inversion */
90 /* Disable output of HSYNC during VSYNC period */
93 /* Disable output of VSYNC during VSYNC period */
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/media/i2c/ |
| H A D | tvp7002.txt | 7 - compatible : Must be "ti,tvp7002"
10 - hsync-active: HSYNC Polarity configuration for the bus. Default value when
13 - vsync-active: VSYNC Polarity configuration for the bus. Default value when
16 - pclk-sample: Clock polarity of the bus. Default value when this property is
19 - sync-on-green-active: Active state of Sync-on-green signal property of the
24 - field-even-active: Active-high Field ID output polarity control of the bus.
28 1 = FID output polarity inverted
31 video-interfaces.txt.
44 hsync-active = <1>;
45 vsync-active = <1>;
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| H A D | tvp514x.txt | 3 The TVP5146/TVP5146m2/TVP5147/TVP5147m1 device is high quality, single-chip
5 video formats into digital video component. The tvp514x decoder supports analog-
6 to-digital (A/D) conversion of component RGB and YPbPr signals as well as A/D
7 conversion and decoding of NTSC, PAL and SECAM composite and S-video into
11 - compatible : value should be either one among the following
17 - hsync-active: HSYNC Polarity configuration for endpoint.
19 - vsync-active: VSYNC Polarity configuration for endpoint.
21 - pclk-sample: Clock polarity of the endpoint.
24 media/video-interfaces.txt.
37 hsync-active = <1>;
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| H A D | tda1997x.txt | 1 Device-Tree bindings for the NXP TDA1997x HDMI receiver
6 - RGB 8bit per color (24 bits total): R[11:4] B[11:4] G[11:4]
7 - YUV444 8bit per color (24 bits total): Y[11:4] Cr[11:4] Cb[11:4]
8 - YUV422 semi-planar 8bit per component (16 bits total): Y[11:4] CbCr[11:4]
9 - YUV422 semi-planar 10bit per component (20 bits total): Y[11:2] CbCr[11:2]
10 - YUV422 semi-planar 12bit per component (24 bits total): - Y[11:0] CbCr[11:0]
11 - YUV422 BT656 8bit per component (8 bits total): YCbCr[11:4] (2-cycles)
12 - YUV422 BT656 10bit per component (10 bits total): YCbCr[11:2] (2-cycles)
13 - YUV422 BT656 12bit per component (12 bits total): YCbCr[11:0] (2-cycles)
16 - RGB 12bit per color (36 bits total): R[11:0] B[11:0] G[11:0]
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| H A D | st,st-mipid02.txt | 1 STMicroelectronics MIPID02 CSI-2 to PARALLEL bridge
3 MIPID02 has two CSI-2 input ports, only one of those ports can be active at a
4 time. Active port input stream will be de-serialized and its content outputted
6 CSI-2 first input port is a dual lane 800Mbps per lane whereas CSI-2 second
8 polarity swap. First port also supports data lane swap.
11 YUV420 8-bit, YUV422 8-bit and YUV420 10-bit.
14 - compatible: shall be "st,st-mipid02"
15 - clocks: reference to the xclk input clock.
16 - clock-names: shall be "xclk".
17 - VDDE-supply: sensor digital IO supply. Must be 1.8 volts.
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/display/exynos/ |
| H A D | exynos_dp.txt | 5 -dp-controller node
6 -dptx-phy node(defined inside dp-controller node)
8 For the DP-PHY initialization, we use the dptx-phy node.
9 Required properties for dptx-phy: deprecated, use phys and phy-names
10 -reg: deprecated
12 -samsung,enable-mask: deprecated
13 The bit-mask used to enable/disable DP PHY.
15 For the Panel initialization, we read data from dp-controller node.
16 Required properties for dp-controller:
17 -compatible:
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| /OK3568_Linux_fs/kernel/drivers/video/rockchip/vehicle/ |
| H A D | vehicle_cfg.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
9 #include <media/v4l2-mediabus.h>
10 #include <linux/rk-camera-module.h>
55 * 000 - YUV
56 * 010 - PAL
57 * 011 - NTSC
58 * 100 - RAW
59 * 101 - JPEG
60 * 110 - MIPI
64 * 0 - output is 422
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| /OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/ |
| H A D | rk1808-evb-x4-second.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
7 #include <dt-bindings/display/drm_mipi_dsi.h>
8 #include "rk1808-evb.dtsi"
12 compatible = "rockchip,rk1808-evb-x4", "rockchip,rk1808";
20 power-key {
23 press-threshold-microvolt = <18000>;
27 /delete-node/ &backlight;
28 /delete-node/ &vcc1v8_dvp;
29 /delete-node/ &vdd1v5_dvp;
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| H A D | rk1808-evb-x4.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
7 #include <dt-bindings/display/drm_mipi_dsi.h>
8 #include "rk1808-evb.dtsi"
12 compatible = "rockchip,rk1808-evb-x4", "rockchip,rk1808";
20 power-key {
23 press-threshold-microvolt = <18000>;
27 /delete-node/ &backlight;
28 /delete-node/ &vcc1v8_dvp;
29 /delete-node/ &vdd1v5_dvp;
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| H A D | rk1808-evb-v10.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
7 #include <dt-bindings/display/drm_mipi_dsi.h>
8 #include "rk1808-evb.dtsi"
12 compatible = "rockchip,rk1808-evb-v10", "rockchip,rk1808";
15 …bootargs = "earlycon=uart8250,mmio32,0xff550000 console=ttyFIQ0 root=PARTUUID=614e0000-0000 rootfs…
18 vad-sound {
20 compatible = "rockchip,multicodecs-card";
21 rockchip,card-name = "rockchip,rk1808-vad";
28 vol-down-key {
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| /OK3568_Linux_fs/u-boot/drivers/video/ |
| H A D | am335x-fb.h | 2 * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at> -
3 * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
5 * SPDX-License-Identifier: GPL-2.0+
30 * 0 = DE is low-active
31 * 1 = DE is high-active
34 * 0 = pix-clk is high-active
35 * 1 = pic-clk is low-active
38 * 0 = HSYNC is active high
42 * 0 = VSYNC is active high
43 * 1 = VSYNC is active low
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| /OK3568_Linux_fs/u-boot/board/freescale/common/ |
| H A D | diu_ch7301.c | 9 * SPDX-License-Identifier: GPL-2.0+
27 * Set VSYNC/HSYNC to active high. This is polarity of sync signals
28 * from DIU->DVI. The DIU default is active igh, so DVI is set to
29 * active high.
42 /* Exit Power-down mode */
45 /* Monitor polarity is handled via DVI Sync Polarity Register */
69 /* Set Sync polarity register */ in diu_set_dvi_encoder()
74 puts("I2C: failed to select dvi syc polarity\n"); in diu_set_dvi_encoder()
|
| /OK3568_Linux_fs/kernel/arch/arm/boot/dts/ |
| H A D | rk3288-evb-android-rk818-mipi-edp.dts | 4 * This file is dual-licensed: you can use it either under the terms
43 /dts-v1/;
44 #include "rk3288-evb.dtsi"
45 #include "rk3288-android.dtsi"
48 compatible = "rockchip,rk3288-evb-android-rk818", "rockchip,rk3288";
50 sdio_pwrseq: sdio-pwrseq {
51 compatible = "mmc-pwrseq-simple";
53 clock-names = "ext_clock";
58 * - SDIO_RESET_L_WL_REG_ON
59 * - PDN (power down when low)
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| H A D | rv1126-rmsl.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/display/drm_mipi_dsi.h>
7 #include <dt-bindings/input/input.h>
11 compatible = "regulator-fixed";
12 regulator-name = "vcc5v0_sys";
13 regulator-always-on;
14 regulator-boot-on;
15 regulator-min-microvolt = <5000000>;
16 regulator-max-microvolt = <5000000>;
19 vdd_arm: vdd-arm {
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| H A D | rk3288-evb.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/input/input.h>
4 #include <dt-bindings/pwm/pwm.h>
13 adc-keys {
14 compatible = "adc-keys";
15 io-channels = <&saradc 1>;
16 io-channel-names = "buttons";
17 keyup-threshold-microvolt = <1800000>;
19 button-up {
22 press-threshold-microvolt = <100000>;
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| H A D | rk3288-evb-android-rk818-lvds.dts | 4 * This file is dual-licensed: you can use it either under the terms
43 /dts-v1/;
44 #include "rk3288-evb.dtsi"
45 #include "rk3288-android.dtsi"
48 compatible = "rockchip,rk3288-evb-android-rk818", "rockchip,rk3288";
50 sdio_pwrseq: sdio-pwrseq {
51 compatible = "mmc-pwrseq-simple";
53 clock-names = "ext_clock";
58 * - SDIO_RESET_L_WL_REG_ON
59 * - PDN (power down when low)
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| H A D | rk3288-evb-android-rk818-edp.dts | 4 * This file is dual-licensed: you can use it either under the terms
43 /dts-v1/;
44 #include "rk3288-evb.dtsi"
45 #include "rk3288-android.dtsi"
48 compatible = "rockchip,rk3288-evb-android-rk818", "rockchip,rk3288";
50 sdio_pwrseq: sdio-pwrseq {
51 compatible = "mmc-pwrseq-simple";
53 clock-names = "ext_clock";
58 * - SDIO_RESET_L_WL_REG_ON
59 * - PDN (power down when low)
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/media/ |
| H A D | video-interfaces.txt | 4 ---------------
21 #address-cells = <1>;
22 #size-cells = <0>;
37 a common scheme using '#address-cells', '#size-cells' and 'reg' properties is
41 specify #address-cells, #size-cells properties independently for the 'port'
44 Two 'endpoint' nodes are linked with each other through their 'remote-endpoint'
53 a device is partitioned into multiple data busses, e.g. 16-bit input port
54 divided into two separate ITU-R BT.656 8-bit busses. In such case bus-width
55 and data-shift properties can be used to assign physical data lines to each
59 --------------------------------
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| /OK3568_Linux_fs/kernel/drivers/gpu/drm/bridge/adv7511/ |
| H A D | adv7511.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
62 #define ADV7511_REG_GC(x) (0x4b + (x)) /* 0x4b - 0x51 */
66 #define ADV7511_REG_AVI_INFOFRAME(x) (0x55 + (x)) /* 0x55 - 0x6f */
70 #define ADV7511_REG_AUDIO_INFOFRAME(x) (0x73 + (x)) /* 0x73 - 0x7c */
77 #define ADV7511_REG_AN(x) (0xb0 + (x)) /* 0xb0 - 0xb7 */
80 #define ADV7511_REG_BKSV(x) (0xc0 + (x)) /* 0xc0 - 0xc3 */
84 #define ADV7511_REG_BSTATUS(x) (0xca + (x)) /* 0xca - 0xcb */
89 #define ADV7511_REG_SYNC_ADJUSTMENT(x) (0xd7 + (x)) /* 0xd7 - 0xdc */
244 * enum adv7511_sync_polarity - Polarity for the input sync signals
245 * @ADV7511_SYNC_POLARITY_PASSTHROUGH: Sync polarity matches that of
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| /OK3568_Linux_fs/kernel/drivers/gpu/drm/stm/ |
| H A D | ltdc.c | 1 // SPDX-License-Identifier: GPL-2.0
41 #define CRTC_MASK GENMASK(NB_CRTC - 1, 0)
55 #define REG_OFS (ldev->caps.reg_ofs)
116 #define GCR_PCPOL BIT(28) /* Pixel Clock POLarity-Inverted */
117 #define GCR_DEPOL BIT(29) /* Data Enable POLarity-High */
118 #define GCR_VSPOL BIT(30) /* Vertical Synchro POLarity-High */
119 #define GCR_HSPOL BIT(31) /* Horizontal Synchro POLarity-High */
132 #define GC1R_IPP BIT(26) /* IRQ Polarity Programmable */
133 #define GC1R_SPP BIT(27) /* Sync Polarity Programmable */
140 #define GC2R_DVAEN BIT(2) /* Dual-View Ability ENabled */
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| /OK3568_Linux_fs/kernel/drivers/gpu/drm/panel/ |
| H A D | panel-ilitek-ili9322.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 * - 8-bit serial RGB interface
7 * - 24-bit parallel RGB interface
8 * - 8-bit ITU-R BT.601 interface
9 * - 8-bit ITU-R BT.656 interface
10 * - Up to 320RGBx240 dots resolution TFT LCD displays
11 * - Scaling, brightness and contrast
19 * Derived from drivers/drm/gpu/panel/panel-samsung-ld9040.c
48 * High voltage on the communication signals, from 0.37 (0x00) to
63 /* 0 = right-to-left, 1 = left-to-right (default), horizontal flip */
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