1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at> - 3*4882a593Smuzhiyun * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef AM335X_FB_H 9*4882a593Smuzhiyun #define AM335X_FB_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define HSVS_CONTROL (0x01 << 25) /* 12*4882a593Smuzhiyun * 0 = lcd_lp and lcd_fp are driven on 13*4882a593Smuzhiyun * opposite edges of pixel clock than 14*4882a593Smuzhiyun * the lcd_pixel_o 15*4882a593Smuzhiyun * 1 = lcd_lp and lcd_fp are driven 16*4882a593Smuzhiyun * according to bit 24 Note that this 17*4882a593Smuzhiyun * bit MUST be set to '0' for Passive 18*4882a593Smuzhiyun * Matrix displays the edge timing is 19*4882a593Smuzhiyun * fixed 20*4882a593Smuzhiyun */ 21*4882a593Smuzhiyun #define HSVS_RISEFALL (0x01 << 24) /* 22*4882a593Smuzhiyun * 0 = lcd_lp and lcd_fp are driven on 23*4882a593Smuzhiyun * the rising edge of pixel clock (bit 24*4882a593Smuzhiyun * 25 must be set to 1) 25*4882a593Smuzhiyun * 1 = lcd_lp and lcd_fp are driven on 26*4882a593Smuzhiyun * the falling edge of pixel clock (bit 27*4882a593Smuzhiyun * 25 must be set to 1) 28*4882a593Smuzhiyun */ 29*4882a593Smuzhiyun #define DE_INVERT (0x01 << 23) /* 30*4882a593Smuzhiyun * 0 = DE is low-active 31*4882a593Smuzhiyun * 1 = DE is high-active 32*4882a593Smuzhiyun */ 33*4882a593Smuzhiyun #define PXCLK_INVERT (0x01 << 22) /* 34*4882a593Smuzhiyun * 0 = pix-clk is high-active 35*4882a593Smuzhiyun * 1 = pic-clk is low-active 36*4882a593Smuzhiyun */ 37*4882a593Smuzhiyun #define HSYNC_INVERT (0x01 << 21) /* 38*4882a593Smuzhiyun * 0 = HSYNC is active high 39*4882a593Smuzhiyun * 1 = HSYNC is avtive low 40*4882a593Smuzhiyun */ 41*4882a593Smuzhiyun #define VSYNC_INVERT (0x01 << 20) /* 42*4882a593Smuzhiyun * 0 = VSYNC is active high 43*4882a593Smuzhiyun * 1 = VSYNC is active low 44*4882a593Smuzhiyun */ 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun struct am335x_lcdpanel { 47*4882a593Smuzhiyun unsigned int hactive; /* Horizontal active area */ 48*4882a593Smuzhiyun unsigned int vactive; /* Vertical active area */ 49*4882a593Smuzhiyun unsigned int bpp; /* bits per pixel */ 50*4882a593Smuzhiyun unsigned int hfp; /* Horizontal front porch */ 51*4882a593Smuzhiyun unsigned int hbp; /* Horizontal back porch */ 52*4882a593Smuzhiyun unsigned int hsw; /* Horizontal Sync Pulse Width */ 53*4882a593Smuzhiyun unsigned int vfp; /* Vertical front porch */ 54*4882a593Smuzhiyun unsigned int vbp; /* Vertical back porch */ 55*4882a593Smuzhiyun unsigned int vsw; /* Vertical Sync Pulse Width */ 56*4882a593Smuzhiyun unsigned int pxl_clk_div; /* Pixel clock divider*/ 57*4882a593Smuzhiyun unsigned int pol; /* polarity of sync, clock signals */ 58*4882a593Smuzhiyun unsigned int pup_delay; /* 59*4882a593Smuzhiyun * time in ms after power on to 60*4882a593Smuzhiyun * initialization of lcd-controller 61*4882a593Smuzhiyun * (VCC ramp up time) 62*4882a593Smuzhiyun */ 63*4882a593Smuzhiyun unsigned int pon_delay; /* 64*4882a593Smuzhiyun * time in ms after initialization of 65*4882a593Smuzhiyun * lcd-controller (pic stabilization) 66*4882a593Smuzhiyun */ 67*4882a593Smuzhiyun void (*panel_power_ctrl)(int); /* fp for power on/off display */ 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun int am335xfb_init(struct am335x_lcdpanel *panel); 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun #endif /* AM335X_FB_H */ 73